Palle Bharath Reddy

Software Engineer

Bengaluru, Karnataka, India4 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in Static Timing Analysis and Physical Design.
  • Proficient in Verilog and Linux environments.
  • Currently working as a Synthesis and STA Engineer.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in timing analysis and physical design.

Contact

LinkedIn

Skills

Core Skills

Static Timing AnalysisPhysical Design

Other Skills

VerilogNI MultisimLinuxShell Scripting

Experience

4 yrs 3 mos
Total Experience
2 yrs 2 mos
Average Tenure
3 yrs 4 mos
Current Experience

Mediatek

Synthesis and STA Engineer

Jan 2023 – Present · 3 yrs 4 mos · Bengaluru, Karnataka, India

Static Timing AnalysisPhysical DesignVerilogNI MultisimLinuxShell Scripting

Rv-vlsi vlsi and embedded systems design center

Physical Design Trainee

Apr 2022 – Oct 2022 · 6 mos · Bengaluru, Karnataka, India

Acd communications pvt ltd

Engineer in Electronics Department

Mar 2021 – Feb 2022 · 11 mos · Hyderabad, Telangana, India

Education

Anurag Group of Institutions

Bachelor of Technology - BTech — electronics and communication engineering

Jan 2016 – Jan 2020

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