Prateek Srivastava — VP of Engineering

I have experience in synthesis, physical design implementation of complex blocks, STA of chip-top, DFT, Low Power Equivalence, logical equivalence, static and dynamic IR , ESD closure, and physical verification (drc, lvs, perc,erc). Presently managing the IP backend signoff team from Qualcomm Noida site. Specialties: Synthesis & PnR (Physical Design). Full rtl to gds flow (synthesis, floor-planning, placement, clock tree synthesis, routing , optimization, noise analysis). STA of chip top and block, Low Power checks & implementation, Logic Equivalence Checks, Advanced STA: SOCV, SSTA, Cross talk, Glitch, Latch timing, Hierarchical solutions, Spice simulations, IR analysis and ESD closure, Physical verification (DRC, LVS, ERC), DFT (pattern generation and delay simulations), Design architecture, TCL scripting.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on Physical Design and Timing Analysis.

Location: Delhi, India

Experience: 18 yrs 5 mos