Priya Mittal

Software Engineer

Delhi, India6 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in VLSI design and verification.
Proficient in multiple programming languages including Python and C++.
Strong background in electronics and computer architecture.

Stackforce AI infers this person is a VLSI Engineer with expertise in ASIC design and verification.

Contact

Skills

Core Skills

VerilogFpga

Other Skills

UARTAPBChipscopeXilinxSystem VerilogCC++PythonPerlMachine learningComputer visionAnalog electronicsDigital electronicsVLSIComputer architecture

About

An ambivert engineer and a curious learner! VLSI is my principle area of interest. Besides that, I like to dance, write and sketch. I firmly believe that empathy and ambition, working together, can create magic. Technical Skills 1. HDLs/ HVLs: Verilog HDL, VHDL, System Verilog(amateur level) 2. Programming/Scripting languages : C, C++, Python, Perl 3. Machine learning, Computer vision (amateur level) 4. Well versed with Analog, Digital electronics, VLSI and computer architecture concepts I am always up for learning new things and interacting with new people. If you want to discuss a project, have any exciting idea/news to share or want to discuss any possible collaboration, hit me up! I'd be more than happy to talk.

Experience

6 yrs 9 mos

Total Experience

2 yrs 3 mos

Average Tenure

3 yrs 7 mos

Current Experience

Nvidia

ASIC Verification Engineer

Oct 2022 – Present · 3 yrs 7 mos

Western digital

3 roles

Senior Engineer

Jul 2022 – Sep 2022 · 2 mos · India

Engineer

Aug 2020 – Jul 2022 · 1 yr 11 mos · India

ASIC Development Engineering Intern

Jun 2019 – Jul 2019 · 1 mo · Bengaluru, Karnataka

1. Designed and implemented UART (Universal Asynchronous Receiver Transmitter) on an ASIC prototyping system with Virtex-7 FPGA
2. Incorporated APB (AMBA Peripheral Bus) protocol in the design
3. Debugged the design using Chipscope in Xilinx

VerilogFPGAUARTAPBChipscopeXilinx

Genelek technologies

Hardware Engineering Intern

Dec 2018 – Jan 2019 · 1 mo

Defence research and development organisation (drdo)

Trainee

Jun 2018 – Jul 2018 · 1 mo

1. Worked on one of the DRDO's on-going project and made use of RS232 communication protocol to undergo serial communication.
2. Interfaced LCD display and matrix keypad with device, making it user friendly.
3. Designed and etched an accurately sized PCB including all the components of the controller, making it easy to access and useful from industry point of view.

University student internship program, dtu

Intern

Jun 2017 – Sep 2018 · 1 yr 3 mos

1. Assisted in the university's new endeavour, i.e, the Bluetooth attendance app under Prof. SK Garg( Pro Vice Chancellor, DTU)
2. Worked for 2 consecutive years in JAC admission processes, helping streamline the admissions of more than 18,000 students.
3. Maintained the database of over 30,000 including both the faculty and students.