Rahul Jain — Product Engineer

-> 5+ years of experience in MIXED SIGNAL Design IP's -> Years of experience in SoC Design and integration -> 18+ year of professional experience in hardware design and development of ASIC products -> Extensive experience in micro architecture design, logic design and RTL Implementation in Verilog HDL from scratch for required standard/specification. -> Experience in design flow automation , helped to reduce "time to market" -> Strong knowledge in High speed SERDES PHY's -> Specialist in decision feedback equalization (DFE) in SERDES -> Developed Micro-architecture, successfully designed and implemented DFE PHY 8G/10G -> Experience in handing multiple projects -> Excellent knowledge in STA/Lint/CDC analysis -> Experience in SDF back annotation simulation (GLS) -> Experience in customer support Verification - -> Developed new testcases to hit code coverage more than 95% -> Successful track record of working on new flows and methodologies and proven record of producing high quality work ahead of schedule. -> Expert in ramping up team/project, hiring, work delegation, objective setting and performance evaluation and overall project managemen -> Excellent ability to communicate with all departments in a design cycle Specialties:* Verilog for RTL coding. Cadence -Verilog-XL, NC – Verilog, Modelsim for RTL/netlist simulation - RC for synthesis - ET for DFT , ATPG vector generation , scan chain insertion - ETS for STA Synopsys – DC for Synthesis CVS and SVN for Data management Paper - http://www.design-reuse.com/articles/18135/system-packet-interface-spi-4-2-ip-core.html Visit my blog to know more on VLSI Blog - http://rtldigitaldesign.blogspot.in/

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in ASIC and mixed signal design.

Location: Bengaluru, Karnataka, India

Experience: 21 yrs 1 mo