Rajeev Mishra

Software Engineer

Delhi, India15 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SoC RTL Integration and Synthesis.
Led 5G modem implementation projects.
Proficient in Static Timing Analysis and Low Power Design.

Stackforce AI infers this person is a Telecommunications expert with a strong focus on SoC design and implementation.

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Skills

Core Skills

Soc Rtl IntegrationSynthesisRtl DesignStatic Timing Analysis

Other Skills

ASICApplication-Specific Integrated Circuits (ASIC)CC++Connectivity of BlocksConstraints DevelopmentConstraints PreparationDFTDesign VerificationDigital Circuit DesignEclipseEldoFlow SetupImplementationJava

About

Experienced in Design Implementation (Gate level Synthesis), Constraints Preparation, Static Timing Analysis, Implementing Low power (UPF) on multiple blocks throughout the trial and tape-out phases of the projects, RTL Integration at SoC level, Logical Equivalence checks, Quality checks of Netlist, Clock Domain Crossing (CDC) at SoC level. Worked on the 5G modem implementation activities owning the full implementation tasks like synthesis, constraints, low power checks, logical equivalence checks etc. In the Past have worked on SoC RTL Integration, integration various subsystems and responsible for generation of compile clean SoC level RTL. Generating the Partitioned RTL (Tiling), Doing connectivity of various blocks, Getting various Collateral's required to be delivered to DV team. Reviewing the PLDRC reports and fixing Design bugs at SoC level. ECO implementation after code freeze. Skill set: Implementation/Synthesis, STA, Logical equivalence checking, SOC RTL Integration, DRC cleanup, CDC, RTL Partitioning Low Power Checks, Front end Design Flow, ECO. Tools : Design Compiler(DC), Fusion Compiler(FC), Genus (RC), Conformal, Primetime, Modelsim, VCS, Novas, Verdi, Defacto.

Experience

Qualcomm

4 roles

Senior Staff Engineer/Manager

Promoted

Dec 2024 – Present · 1 yr 4 mos

Staff Engineer

Dec 2021 – Nov 2024 · 2 yrs 11 mos

Senior Lead Engineer

Promoted

Dec 2018 – Nov 2021 · 2 yrs 11 mos

Involved in the synthesis/implementation of the modem subsystems (5G/LTE) along with SoC blocks. Worked in the constraints development and also cleaning up the clp checks along with the FV cleanup as well. Worked as SoC Integration lead for 3 SoCs managing the SoC RTL generation and also cleaning up the lint issues and delivering the clean RTL to design verification team. Working closely with the DFT/PD/DV team. Responsible for delivering the SoC RTL by integrating and connecting different IP's. Reviewing the CDC/PLDRC reports. Generating the Collaterals which are required for various teams. Doing ECO, Bug fixes

SynthesisImplementationConstraints DevelopmentLint Issue CleanupSoC IntegrationLogical Equivalence Check+2

Senior Engineer

Apr 2016 – Nov 2018 · 2 yrs 7 mos

Part of SoC RTL Integration Team. Responsible for Integrating various cores at SoC Level, Doing Connectivity of Blocks, RTL Restructuring (TIling), Memory Generation at SoC Level. Generating the Top Level RTL with compilation clean checks. Providing support to DV team.

SoC RTL IntegrationConnectivity of BlocksRTL RestructuringMemory GenerationRTL Design

Cadence design systems

Lead Engineer

Aug 2015 – Feb 2016 · 6 mos · Noida Area, India

Worked for Multimode Multi Corner timing, creating benchmarks of MMMC, flow setup of MMMC, SDC command validation.

Timing BenchmarksFlow SetupSDC Command Validation

Stmicroelectronics

Senior Design Engineer

Jun 2014 – Aug 2015 · 1 yr 2 mos · Noida Area, India

Synthesis of clockgen for 28nm fdsoi and RTL integration of Bootdevice Block for SoC.
Responsibilities Include:
Logic Generation and Synthesis of clockgen block using DC (Design Compiler).
Understanding of Clocks, Constraints preparation for synthesis.
Running Logical Equivalence Check (LEC) from RTL to final netlist.
Running Static Timing Analysis (STA) on Post layout netlist leading to block closure.
Running Netlist quality checks.
Running CDC at SoC level.

SynthesisRTL IntegrationStatic Timing AnalysisLogical Equivalence Check

Pmc-sierra

Design Implementation Engineer

Jul 2012 – May 2014 · 1 yr 10 mos · Bangalore

Responsibilities Include:
Synthesis of PCIe subsystem using RC (RTL Compiler).
Understanding of Clocks, Constraints preparation for synthesis and STA.
Scan chain stitching of generated netlist.
Low power implementation for generated netlist using CLP (Conformal low power).
Running Logical Equivalence Check (LEC) from RTL to final netlist.
MBR Conversion of Netlist.
Running Static Timing Analysis (STA) on Post layout netlist leading to block closure.

SynthesisConstraints PreparationStatic Timing AnalysisLow Power Implementation