Yogaraj Selvalingam

Software Engineer

Eindhoven, North Brabant, Netherlands10 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 10 years of experience in ASIC Functional Verification.
Expert in UVM and System Verilog Testbench development.
Proven track record in functional verification of complex protocols.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC and protocol verification.

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Skills

Core Skills

Functional VerificationUsb ProtocolsAsic VerificationUvmDdr3 Sdram

Other Skills

APB BridgeASICApplication-Specific Integrated Circuits (ASIC)CC++FPGAField-Programmable Gate Arrays (FPGA)Functional CoverageI2CLinuxLogic SynthesisOOPsPerlPower Management UnitProtocols - AHB - LITE

About

A self-motivated, team playing and result oriented professional having 10+ years of relevant experience in ASIC Functional Verification with an excellent communication skill, leadership quality & logical skill set. ✓ Experience in Soc, Subsystem and IP Verification. ✓ Experience in UVM and technical languages such as System Verilog HVL and Verilog HDL. ✓ Experience in developing UVM and System Verilog Testbench from scratch. ✓ Experience in writing test plans, coverage plans and Debugging RTL. ✓ Experience in Constraint Random Verification and Functional & Code coverage. ✓ Worked on standard protocols like USB 3.2, USB 2.0, Flash, DDR3 SDRAM. ✓ Worked on bus protocols like AMBA AXI, AHB-LITE and APB. ✓ Experience in interacting with Design Architects and Designers. Software & Protocol Skill Sets: Platform : Linux, Windows HDL : Verilog HVL : System Verilog Methodology : UVM Standard Protocols : AMD Infinity Fabric, USB 3.2, USB 2.0, DDR3 SDRAM, Flash Bus Protocols : AMBA AXI, AHB-Lite, APB Tools : VCS, NCSIM and Questasim. Script : Python Specialties: ASIC Verification using System Verilog HVL & UVM.

Experience

Nxp semiconductors

Senior Digital Verification Engineer

Aug 2022 – Present · 3 yrs 7 mos · Netherlands

Amd

Senior Silicon Design Engineer

Jan 2021 – Jul 2022 · 1 yr 6 mos · Bengaluru, Karnataka, India

Infinity Fabric, the successor to AMD HyperTransport, is a high speed interlink used for data exchange between the CPU, PCIe, I/O, and memory. AMD’s Infinity Fabric design consists of two distinct parts: Scalable Control Fabric (SCF) and Scalable Data Fabric (SDF). The SDF includes power management, security, and anything involving maintaining the operation of the chip while the SCF is what ties the memory and the compute components together.

Synopsys inc

ASIC DIgital Design Verification Engineer II

Jan 2018 – Dec 2020 · 2 yrs 11 mos · Bengaluru Area, India

The Universal Serial Bus is the most common type of computer port used in today's computers. USB 3.2 is primarily a performance enhancement to USB 3.1 to provide more bandwidth for devices. The USB 3.2 speeds up to 20 Gbps by the introduction of two lanes in the architecture whereas the existing USB 3.1 which had one lane and speeds upto 10 Gbps. With the help of USB you can connect up to 127 peripherals to a single port. The USB 3.2 standard is backward compatible with USB 3.1/3.0 and USB 2.0.
Responsibilities:
Worked on Functional verification of Link & Protocol Layer.
Worked on designing checker for Power Management Unit of USB 3.2 & 3.1.
Worked on different customer configuration needs.
Worked on Functional Coverage for xHCI to improve it above 95%.
Worked on enhancing the existing USB 3.1 test bench to USB 3.2 test bench environment.

Functional verificationUSB 3.2Power Management UnitFunctional CoverageTest bench enhancementFunctional Verification+1

Ignitarium

ASIC Verification Engineer

Nov 2016 – Dec 2017 · 1 yr 1 mo · Bangalore

The Canaveral SoC is a Microcontroller platform based on ARM Cortex Teal Processor. This IOT platform is used for various applications from segments like Healthcare, Automotive, Radio etc. Building a generic platform that can be used as a starting point for multiple derivatives. All Design and Verification environment should be generic enough to meet this requirement.
Responsibilities:
Created Test Plan for Cache_Flash Subsystem and developed UVM Test Cases for the same.
Created Monitors & Scoreboards for multiple Module IPs and Interface IPs.
Created associated Environment for above checkers and Integrated with System Level TB.
Created Functional coverage plan for Flash IP Controller and coded coverage for the same.
Worked on developing Code Coverage to improve it above 95%.

Test Plan CreationUVM Test CasesFunctional CoverageASIC VerificationUVM

Hcl technologies

ASIC Verification Engineer

May 2015 – Aug 2016 · 1 yr 3 mos · Bengaluru Area, India

The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM. Read and Write operation to the DDR3 SDRAM are burst oriented. Operation begins with the registration of an Active command, which is then followed by a Read or Write command.
Responsibilities:
Created Verification Architecture in UVM for DDR3 SDRAM Controller.
Created Test Cases for Initialization, Command Interface and Write Interface.
Created UVM TB Environment components and its integration.

Verification ArchitectureUVMTest CasesASIC VerificationDDR3 SDRAM