Rajni Bhatia — Software Engineer
STA and Synthesis Engineer at Qualcomm. Previously worked as Product Validation Engineer II at Cadence in AVIP Team. Masters focused in VLSI from IIIT-Delhi
Stackforce AI infers this person is a VLSI and ASIC design engineer with strong expertise in timing analysis and synthesis.
Location: Delhi, India
Experience: 6 yrs 10 mos
Skills
- Static Timing Analysis
- Floorplanning
Career Highlights
- Expert in Static Timing Analysis and Floorplanning.
- Strong background in VLSI and ASIC design.
- Proven experience in product validation and engineering.
Work Experience
Qualcomm
Senior Engineer (1 yr 7 mos)
STA and Synthesis Engineer (2 yrs)
Cadence Design Systems
Product Validation Engineer II (1 yr 5 mos)
Indraprastha Institute of Information Technology, Delhi
Teaching Assistant (1 yr 10 mos)
Delhi Metro Rail Corporation Ltd
Summer Intern (2 mos)
Education
Master of Technology - MTech at Indraprastha Institute of Information Technology, Delhi
Bachelor of Technology - BTech at Maharaja Surajmal Institute Of Technology
