Rakeshkumar S. — Product Engineer

SUMMARY OF SKILLS • Over 11 years of engineering experience that covers multiple aspects of ASIC/SoC/IP Verification. Expertise at handling multiple projects, multiple protocols, and working with clients in different time zones at a time within a single organization. Mentoring entry-level engineers and helping organizations to grow in terms of improving the quality of verification solutions delivered to the market. • In-depth knowledge of entire chip design process including IP/SoC Verification Flow, Micro-architecture features, PCIe Express (Gen 1 to Gen 5), CXL 1.1 IP and SoC Verification, IA32 architecture CPU Verification and Validation. Developing complete UVM testbench from scratch after understanding the design specifications, Expertise at developing Test Plan and Function Coverage Plan looking at the design specification. Proficient at Functional Coverage and Code Coverage analysis and providing feedback to the verification team. Expertise at root causing regression failures to Test Issues, Environment Issues, and RTL bugs in shorter duration. • Extensive hands-on experience in RTL design verification using System-Verilog and UVM Methodology. • In-depth knowledge of IA32 Architecture, PCIe Express Protocol(PCIe Gen 1 to PCIe Gen 4). Having a basic understanding of PCIe Gen 5 and CXL 1.1 protocols. Complete knowledge related to PCIe protocol enhancements targeted towards server domain(PCIe SR-IOV, PCIe MR-IOV, and PCIe NVMe). Ramping up on solutions like USB over PCIe. • Significantly contributed to Industry-standard protocol development forums. – PCIe Express(PCI SIG Member) • Collaborative team player with strong technical, communication, and problem-solving skill. TECHNICAL PROFICIENCIES: • Programming/Scripting Languages: Verilog, System Verilog, C, C++, TCL, Perl. • VIP(Verification IP Development): PCIe Gen 3 TL Layer VIP module owner, PCIe SR_IOV VIP solution architect and developer, PCIe Physical Layer 8b/10b encoder/decoder VIP architect and developer, PCIe Gen 3 Physical Layer LTSSM(FSM) module development architect and developer(LTSSM Specific Verification), Resolving VIP bugs filed by customers in shorter duration, Helping customers to verify the initial version of RTL with hotfixes. • Protocols: IA32 CPU Architecture, PCIe Gen1 to Gen5, CXL 1.1, PCIe NVMe, PCIe SR_IOV, PCIe MR_IOV • Methodology: UVM, • Tools: Synopsys VCS, ModelSim, Verdi, DVE, Verdi, Design Compiler, FPGA debugger, Protocol Analyzer, Logic Analyzers, debugger, and Oscilloscopes, Mentor Tools, Cadence NCsim, Cadence vManager, Cadence Xillium Simulator.

Stackforce AI infers this person is a VLSI Verification Engineer with extensive experience in ASIC and SoC design.

Location: Bengaluru, Karnataka, India

Experience: 15 yrs 5 mos

Skills

Pcie Verification
Team Leadership
Verification Engineering
Soc Verification
Cpu Verification
Vip Development
System Validation

Career Highlights

Over 11 years of ASIC/SoC/IP Verification experience.
Expertise in PCIe protocols from Gen 1 to Gen 5.
Strong mentoring skills for entry-level engineers.

Work Experience

AMD

SMTS Silicon Design Engineer (4 yrs 4 mos)

Wipro Limited

VLSI Lead Engineer (3 yrs 8 mos)

ALTEN Calsoft Labs

Senior Verification Engineer (8 mos)

SeviTech Systems Pvt. Ltd.

Senior Verification Engineer (8 mos)

AMD

Sr. Design Verification Engineer (1 yr)

PerfectVIPs

Sr. ASIC Verification Engineer (2 yrs 7 mos)

California State University, Sacramento

Technical Assistant (6 mos)

Intel Corporation

System Validation Engineer (2 yrs 8 mos)

Advanced Logic Design

Teaching Assistant (3 mos)

Dharmsinh Desai University

Lecturer (0 mo)

Education

MS at California State University-Sacramento

Bachelor at Dharmsinh Desai University

Rakeshkumar S.

Product Engineer

Bengaluru, Karnataka, India15 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 11 years of ASIC/SoC/IP Verification experience.
Expertise in PCIe protocols from Gen 1 to Gen 5.
Strong mentoring skills for entry-level engineers.

Stackforce AI infers this person is a VLSI Verification Engineer with extensive experience in ASIC and SoC design.

Contact

Skills

Core Skills

Pcie VerificationTeam LeadershipVerification EngineeringSoc VerificationCpu VerificationVip DevelopmentSystem Validation

Other Skills

PCIe Gen 1/2/3 architecture verificationCode CoverageFunctional CoveragePCIe protocol debugVideo architecture verificationTest plan closureIntegration of new blocksPCIe SOC plan developmentMMU SOC plan developmentIntegration of VIPsClient requirement gatheringUVM methodologyTest plan developmentDebuggingVIP BFM implementation

About

Experience

15 yrs 5 mos

Total Experience

2 yrs

Average Tenure

4 yrs 4 mos

Current Experience

Amd

SMTS Silicon Design Engineer

Jan 2022 – Present · 4 yrs 4 mos · Bengaluru, Karnataka, India

I am part of performance verification team to measure performance for NBIO and CPU performance..

Wipro limited

VLSI Lead Engineer

May 2018 – Jan 2022 · 3 yrs 8 mos · Bengaluru Area, India

Working with Intel PCIe Client:
1) Verification of PCIe Gen 1/2/3 architecture.
2) Working on Code Coverage and Functional Coverage of PCIe TL Layer Modules.
3) Leading the team of 5 people to achieve success in project.
4) Working on PCIe features like PTM, IOSF, LTR, OCQ and All_Supported.
5) Working on a PCIe protocol debug.
Working with Intel PCH SOC team:
1) Working on DTS/TT block for verification.
2) Debugging the test cases for SOC.

PCIe Gen 1/2/3 architecture verificationCode CoverageFunctional CoverageTeam leadershipPCIe protocol debugPCIe Verification+1

Alten calsoft labs

Senior Verification Engineer

Sep 2017 – May 2018 · 8 mos · Bengaluru Area, India

I am working in Alten Calsoft as Senior Verification Engineer. I am working in Qualcomm as Client.
1) Working in Video SS group to verify latest video architecture.
2) Working closely with designers to close the testplan of video group.
3) Working on an integration of new blocks in debug modules.

Video architecture verificationTest plan closureIntegration of new blocksVerification Engineering

Sevitech systems pvt. ltd.

Senior Verification Engineer

Jul 2016 – Mar 2017 · 8 mos · Banglore

Client: Samsung India Research Private Limited..
1) Working on developing the PCIe SOC plan. Integrating the PCIe VIP on platform.
2) Working on developing the MMU SOC plan. Integrating the MMU VIP on platform.
3) Working on a Samsung security block for SOC. Developing subsystem and SOC level testplan.
4) Working on integrating of I2C, UART, SPI and QSPI VIPs.
5) Working on Samsung security block subsystem and SOC level verification.
6) Working with client directly to gather the requirements.

PCIe SOC plan developmentMMU SOC plan developmentIntegration of VIPsClient requirement gatheringSOC Verification

Amd

Sr. Design Verification Engineer

Sep 2015 – Sep 2016 · 1 yr · Hyderabad Area, India

Focusing on verification of upcoming CPU's targeted towards SOC's, Desktop,Laptops and Gaming Consoles. Mainly using UVM methodology,assembly and C++ env.
1) Work on latest AMD processor debug with directed and random test cases.
2) Work on performance analysis between two families of processors.
3) Work on developing the testplan and testcases.
4) Working with designers to layout test plan for new features. Developing test cases and running regressions.
5) Working with SOC team to debug issues found in overall design.
6) Total focus on a x86 architecture debug and verification.

CPU verificationUVM methodologyTest plan developmentDebuggingCPU Verification

Perfectvips

Sr. ASIC Verification Engineer

Feb 2013 – Sep 2015 · 2 yrs 7 mos · India

VIP BFM implementation of PCIe Gen 3:
1) Understanding requirements of PCIe Gen 3 spec changes from Gen 2 spec version in terms of Phy layer.
2) Implementing the logic to perform 128b/130b encoding.
3) Verifying the functionality of implementation with back to back VIP mode in both SNPS VCS
and Cadence NCSIM simulators.
SR_PCIM driver(RC side) and SR-IOV EP VIP Implementation:
1) Understanding requirements of virtual and physical function for Endpoint VIP.
2) Implementation of SR_IOV extended configuration space logic for Endpoint VIP in SV.
3) Understanding SR_PCIM driver and implementing it from RC to configure Endpoint VIP in SV.
4) Verifying SR_IOV feature in VIP-VIP back to back mode in SNPS VCS and Cadence NCSIM
simulator.
5) Written test plan for verifying all the SR_IOV features including configuration space, power
management and non posted transaction expectation.
PCIe 3.0 TL Layer test cases implementation:
1) Developed test plan from PCIe 3.0 spec for all TL Layer spec feature.
2) Implementing TL Layer test cases in UVM methodology including error injection scenarios.
3) Verifying all TL Layer tests in VIP-VIP and VIP-IIP mode. Making sure test works in both env.
4) Verifying the functional coverage of all the tests and adding tests to fil the gaps.
5) Helping monitor team to identify the important general protocol check for implementation.
6) Implementing the overall enviournment to interface VIP and DUT for running test.
SOP(SCSI Over PCIe) VIP Implementation(UVM Env) :
1) Understood SCSI over PCIe protocol with host and target implementation.
2) Implemented UVM enviournment as host and target agents of SOP.
3) Implemented all the SCSI commands to be executed in host driver.
4) Implemented all the SCSI commands response from target in target driver.
5) Verified SOP UVM enviournment in VIP back to back mode.
6) Written test plan for verifying host and target env.

VIP BFM implementationPCIe Gen 3 verificationSR-IOV VIP implementationTest plan writingVIP Development

California state university, sacramento

Technical Assistant

Jun 2009 – Dec 2009 · 6 mos

I was technical assistant in california state university,sacramento.My duties included conducting lab experiments on FPGA chips.

Intel corporation

System Validation Engineer

Feb 2009 – Oct 2011 · 2 yrs 8 mos · Folsom

in debugging IA32 architecture related to interrupt, faults, task management, protection related issues.
Experience in debugging cache coherency and consistency related issues.
Experience in developing test plans in C for new CPU related features.
Experience in majoring coverage for tests and features.
Experience in writing the TCL/Perl scripts for automation.
Experience in using emulation for debugging the issues faster.
Experience in debugging external buses using TLA for observing data.
Experience in using debug tools to look at micro-architectural states.

Debugging IA32 architectureTest plan developmentTCL/Perl scriptingEmulation debuggingSystem Validation