RAVI N

Product Manager

Bengaluru, Karnataka, India6 yrs 11 mos experience

Key Highlights

Expert in ASIC Digital IC Implementation.
Proven track record with leading semiconductor companies.
Strong background in timing analysis and power optimization.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC Digital IC Implementation.

Contact

ravinkumarnayak@gmail.com LinkedIn

Skills

Core Skills

Logical/physical SynthesisDft InsertionPhysical ImplementationStatic Timing AnalysisPhysical DesignLogical Synthesis

Other Skills

PrimetimeTweakerGenus iSpatialInnovus PnRConformal SmartLECPTPXTestkompressAusdiaVerdiPT-ECOICC-2Synopsys PrimetimeInnouvsGenusTempus

About

Extensive working experience specializing in ASIC Digital IC Implementation (Synthesis/STA) in various cutting edge lower technology nodes ( 3NME,4nm,6nm ) with TSMC fabrication foundries. Currently working as design implementation engineer in Camera Image System Processor - ISP division at MediaTek Bengaluru --> Logical / Physical Synthesis --> Constraints development and review --> LEC, Lower Power --> DFT Insertion / DFTC_QA ( SSN ) --> ATPG Pattern Simulation ( EDT ) --> Signoff STA / PreSTA --> Re-routing for manual timing ECO --> Constraints, Netlist QC checks Co-worked with FE/BE/PD engineers to get best predictable performance with lowest Power/Area/Timing. Provide optimal solution to fix congestion, leakage and critical timings in the design. Products : Mediatek ( Dimensity, Chromebook, Dimensity Auto ) , Google ( Pixel SoC ) , TI ( Radar Chip, MCU ) Strong engineering professional with a master of technology (MTech) focused in VLSI from BMS College of Engineering Bengaluru Basavanagudi .

Experience

6 yrs 11 mos

Total Experience

2 yrs 6 mos

Average Tenure

1 yr 11 mos

Current Experience

Latchq semiconductor pvt ltd

2 roles

Lead STA Engineer

Sep 2025 – Present · 9 mos · Bengaluru, Karnataka, India · On-site

Supporting Synthesis/STA team

Senior STA Engineer

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Logical/Physical Synthesis
Constraints development and review
MMMC timing analysis and feedback
Synthesis PPA experiments
DFT insertion and ATPG Coverage
Logical CLP and Fixes
Glitch analysis and fixes
TSO Based auto and Manual ECOs
Re-routing for timing closure

PrimetimeTweakerLogical/Physical SynthesisDFT Insertion

Mediatek

Image Signal Processor - Synthesis/STA Engineer

Jan 2022 – Jun 2024 · 2 yrs 5 mos · Bengaluru, Karnataka, India · On-site

Working with cross functional engineering team to implement and validate synthesized netlist on aspects of timing, area and power for next generation MediaTek chipsets.
Block ownership of ISP blocks leading to production tape-outs.
> Physical aware synthesis/APR
> SSN Based Scan insertion/AutoDFT
> Logical equivalence check (R2N , N2N)
> Conformal Low Power ( ECOs )
> ATPG pattern simulation ( SAF / TDF )
> Coverage Debugging, Vectorless config for IR
> PreSTA and Constraints checking
> Post flat STA( Tweaker ECOs) , MTBF , Post QC
> QC checks
Products :
MediaTek Dimensity SmartPhones
MediaTek Kompanio Chromebook
MediaTek Dimensity Auto
Tools used: Genus iSpatial, Innovus PnR, Conformal SmartLEC, PTPX, Testkompress, Primetime, Tweaker, Ausdia, Verdi , PT-ECO.

Genus iSpatialInnovus PnRConformal SmartLECPTPXTestkompressPrimetime+6

Ifcs technologies private limited

ASIC Physical Design Engineer

Jun 2019 – Jan 2022 · 2 yrs 7 mos · Bengaluru, Karnataka, India · Hybrid

Worked as an Backend ASIC Physical Design
> Performed gate level netlist implementation with DC ( logical synthesis)
> Physical implementation of test chip from gate level netlist to GDS file
> Involved qualifying netlist by analyzing check_design/ERC
> Performed PnR flow logical to physical connection ( floorplaning to routing )
> Performed timing analysis and fixed various violations
> Analyzed QoR report ( congestion) and applied physical constraints to mitigate high level hotspots

ICC-2Synopsys PrimetimePhysical DesignLogical Synthesis