Sasi Kanth Koney

CEO

Bengaluru, Karnataka, India17 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in design automation and signoff.
  • Executed multiple tapeouts from 65nm to 2nm.
  • Proven track record in pioneering first-of-a-kind initiatives.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design and automation.

Contact

LinkedIn

Skills

Core Skills

Design MethodologyDesign AutomationPhysical DesignLow-power DesignIc Design

Other Skills

Competitive benchmarkingTechnology developmentProliferationPower grid generationStatic IR analysisEM analysisPhysical VerificationLow power checksStatic Timing AnalysisDeep sub-micron technologiesTiming analysisIR drop analysisOCVSI effectsAwk

About

- CPU cores design convergence. - Design Methodology & tech enablement. - Expertise in design automation and Signoff. - Proven track record of successfully pioneering multiple first-of-a-kind initiatives. - Executed multiple tapeouts from 65nm to 2nm. - Tech contributor, trainer and a natural mentor!

Experience

17 yrs 9 mos
Total Experience
2 yrs 11 mos
Average Tenure
3 yrs 7 mos
Current Experience

Synopsys inc

Senior Architect - Applications Engineering

Nov 2022 – Present · 3 yrs 7 mos · Bengaluru, Karnataka, India

  • Competitive bench-marking for critical designs at lower nodes, technology development and proliferation.
Competitive benchmarkingTechnology developmentProliferationDesign MethodologyDesign Automation

Intel corporation

Senior Staff Engineer

May 2017 – Nov 2022 · 5 yrs 6 mos · Bengaluru, Karnataka, India

Cadence design systems

Principal Application Engineer

Oct 2016 – May 2017 · 7 mos · Bengaluru, Karnataka, India

Mentor graphics

Application Engineer

Jan 2013 – Sep 2016 · 3 yrs 8 mos · Bangalore

  • Responsible for pre-sales and post-sales activities of Mentor backend solutions.

Texas instruments

Consultant

Aug 2011 – Dec 2012 · 1 yr 4 mos · Banglore, INDIA

  • Power grid generation, Static IR, EM and Dynamic IR analsysis, Physical Verification, Low power checks and STA.
Power grid generationStatic IR analysisEM analysisPhysical VerificationLow power checksStatic Timing Analysis+2

Amd

2 roles

Physical Design Engineer

Jul 2008 – Jul 2011 · 3 yrs

  • Taking the design from netlist stage to GDS using deep sub-micron technologies against all Physical constraints (like Timing analysis,IR drop, OCV, SI effects,etc..,.).
Deep sub-micron technologiesTiming analysisIR drop analysisOCVSI effectsPhysical Design+1

PD Engineer

Jun 2008 – May 2011 · 2 yrs 11 mos

Education

Jawaharlal Nehru Technological University

Master's degree — VLSI Engineering

Jan 2008 – Jan 2010

VEDA IIT

Masters — VLSI

Jan 2008 – Jan 2010

Stackforce found 100+ more professionals with Design Methodology & Design Automation

Explore similar profiles based on matching skills and experience

Dhanashree K

Dhanashree K

Manager -Talent Acquisition

at Mirafra Technologies

Bengaluru, India13 yrs 4 mos exp
VLSIASIC
Rameez KT

Rameez KT

Staff Engineer

at MaxLinear

Bengaluru, India8 yrs 9 mos exp
Universal Verification Methodology (UVM)SystemVerilog
Himanshu Joshi

Himanshu Joshi

Accumulated Expertise

at Career-Wide Experience

Pithoragarh, India0 mo exp
ragava venkata ravi varma

ragava venkata ravi varma

Lead Engineer

at Digicomm Semiconductor

India4 yrs exp
ValidationPCIeAutomationDebugging
Dinesh Reddy

Dinesh Reddy

VLSI Talent Acquisition Specialist

at Cedar International Solutions Pvt Ltd

Bengaluru, India1 yr 1 mo exp
VLSI Talent AcquisitionTechnical Recruiting
Anuradha D.

Anuradha D.

Senior Human Resources Manager

at Applied AI Consulting (AAIC)

India8 yrs 4 mos exp
HR ManagementStrategic HiringHuman Resources (HR)Hiring
Hargovind Sahu

Hargovind Sahu

Principal Engineer

at Arm

Bengaluru, India18 yrs 8 mos exp
SystemVerilogOn-chip communication protocolsDigital IP DevelopmentFPGA ValidationEmulation Techniques
Shreyas M O

Shreyas M O

Senior Silicon Validation Engineer (GPU/System)

at Qualcomm

Bengaluru, India2 yrs 9 mos exp
Pre & Post Silicon ValidationEmbedded SystemsIP verificationDigital ElectronicsVerification Methodologies