Saurabh Dhoble

Software Engineer

Bengaluru, Karnataka, India9 yrs 10 mos experience

Highly Stable

Key Highlights

7+ years of VLSI industry experience.
Expertise in architecting UVM based verification environments.
Passionate about mentoring junior team members.

Stackforce AI infers this person is a VLSI Engineer with strong expertise in ASIC and SoC validation.

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Skills

Core Skills

Performance VerificationUvmSystem Verilog

Other Skills

System Verilog AssertionsAMBA AXIDigital LogicDigital DesignsSV Constraint RandomizationOOPPower and PerformanceFunctional VerificationPerformance TestingSilvaco TCADCadence VirtuosoCadence EncounterRTL CompilerNCSimNC-Verilog

About

I have been involved in developing and executing strategies for SoC Product bring-up and validation, with multiple tape outs and stepping. I have ownership of HW IPs such as Tensor Processing Unit (CPU), AXI DMA, MMU, and Media Decoder, and I collaborate with Arch, Design, and FW teams to drive BKMs for post silicon validation. I also have experience in production line test content creation, test coverage optimization, volume data analytics, test time reduction, at scale deployment, and yield improvements through binning. I have 7+ years of VLSI industry experience, including 5 years of Pre-Silicon Verification of IP and SoC level of Hardware Accelerator used for Inference and Computer Vision applications. I have expertise in architecting and implementing UVM based verification environments from scratch, using System Verilog constraint randomization, assertions, functional and code coverage, and C based DPI for golden reference. I have also worked on verification of L2 Cache, AMBA AXI, APB, and PCIe protocols. I hold a Master's Degree in VLSI Design from VIT University and a Bachelor's Degree in Electronics Engineering from YCCE, Nagpur University. I am passionate about learning new technologies and methodologies, and I enjoy mentoring junior team members.

Experience

9 yrs 10 mos

Total Experience

7 yrs 11 mos

Average Tenure

1 yr 11 mos

Current Experience

Intel technology india pvt ltd

4 roles

CPU Validation Engineer

Jul 2022 – Jul 2024 · 2 yrs

Responsible for CPU validation
Developed hardware validation test strategies, including CPU validation using C/assembly kernels.
Conducted Power & Performance (PNP) Characterization of silicon, utilizing specialized test content to maximize Memory stress & Power consumption.
L2 Cache validation across various feature sets.

Performance Verification

Silicon Validation Engineer

Jan 2021 – Jun 2022 · 1 yr 5 mos

Experience in developing and executing strategies for SoC Product bring-up and validation.
Ownership of HW IPs such as AXI DMA, MMU & Media Decoder.
Production line test content creation, Test coverage optimization, Collaboration with Arch, Design, & FW teams to drive BKMs for post silicon validation.
Volume data analytics, test time reduction, at scale deployment, yield improvements through binning
Silicon test content generation, extensive emulation testing & silicon stress testing & regression.
Root caused multiple HW bugs critical to product cycle development.
Internal & External ownership of RMA debugs & trace analysis.

Pre Silicon Verification Engineer

Jun 2016 – Dec 2020 · 4 yrs 6 mos

Worked on IP/SoC level verification of Hardware Accelerator used for Training & Inference applications.
Experience in architecting & implementing Design Verification infrastructure & executing full verification cycle.
Experience in development of UVM based verification environments from scratch.
Generated verif test plans, test case development for all IP features referring from HW Specs
Used System Verilog constraint randomization to build & enhance test suite to exercise corner cases.
Experience in writing System Verilog Assertions based on HW Spec
Use of C based DPI for golden reference generation.
Implementation of Functional checkers, Perf monitors, AXI protocol checkers in UVM scoreboard
Modified AXI master & Slave BFMs to create corner case Scenarios.
Regression runs, debugs, bugs reporting & coverage analysis.
Experience working across and building relationships with cross-functional teams such as Arch, Design & Post silicon validation teams

System Verilog AssertionsAMBA AXIPerformance VerificationUVMSystem Verilog

Intern

Jul 2015 – May 2016 · 10 mos

The Work Profile of Internship Is Front End RTL Design & Verification. I Implemented & Deployed a K-Means clustering algorithm on a Matrix Multiplication HW Engine to efficiently find out the distance between neighboring data points.