shruti Biradar

Software Engineer

Bengaluru, Karnataka, India6 yrs 10 mos experience

Highly Stable

Key Highlights

Nearly 6 years in advanced-node SOC and ASIC implementation.
Expertise in full-cycle Physical Design and timing closure.
Proficient in leading teams and mentoring junior engineers.

Stackforce AI infers this person is a Physical Design Engineer specializing in ASIC and SoC implementations.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

PNRSTAPVPICadence innovas toolSynopsys primetimesign offTeam LeadershipDebuggingVery-Large-Scale Integration (VLSI)VerilogLogic DesignApplication-Specific Integrated Circuits (ASIC)LinuxTcl-Tk

About

Experience: -> Senior/Lead Physical Design Engineer with nearly 6 years of hands-on expertise in advanced-node SOC, ASIC implementation, delivering multiple successful tape-outs across 3nm, 4nm, 5nm, 6nm, , 7nm,12nm,45nm technologies -> Specialize in full-cycle Physical Design-from floorplanning and placement to CTS, routing, STA, ECO, and signoff-ensuring robust, high-performance silicon under aggressive schedules and complex design constraints. -> My experience spans multi-voltage, ON/OFF, AON, low-power, and macro-dominated blocks with instance couunts up to 3.5M+ allowing me to drive timing closure, congestion clean-up, CLP fixes, DRV/DRC resolution, and PPA improvements at scale. -> Throughout my career, I have played key roles in leading block-level implementations, mentoring junior engineers, and collaborating closely with PE/R&D/AE/STA teams to solve complex design challenges Proficiencies: -> Innovus, ICC2, Fusion Compiler, PrimeTime, Calibre, and Tweaker, supported by strong scripting capabilities (Tcl, Shell) for automation and flow optimization. Core Skills: Floorplanning, low-power design, timing closure, and signoff.