Jul 2019 – Jun 2025 · 5 yrs 11 mos · Bengaluru, Karnataka, India · On-site

• Throughout my carrier at Analog Devices , i got the chance to Learn, Collaborate and Innovate in below SoC design activities:
• RTL Design Integration and Development: Integrated various 3rd party IPs, like xSPI , EMAC , EMMC. Creating SPEC , Block level Integration diagram , SUBSYSTEM wrapper , clock and reset analysis , ramming up DV engineer, DV support, GLS Debugs, etc.
• RTL Validation Techniques (LINT, CDC , RDC) : Creating these Flows to closing LINT CDC analysis with 0 violations.
• Logical Equivalence Checks (LEC) for incremental modified RTL Design. ( RTL vs RTL Lec)
• Gate Level Simulations and Debugs.
• Static Timing Analysis (Chip-Top timing Analysis, TCL Scripting , SDF generation, Leakage recovery , Hands on experience on ECO flow , Constraints Feedback , AC-Timing Closure for various High Speed peripherals like LPDDR4 , EMMC , EMAC ,xSPI)
• Design Verification - Block level and Integration DV ( Test Plan Creation, Directed Test Vectors and scenarios, UVM Based checks, Formal Connectivity checks , Full chip regression cleanup , Performance DV ,Code Coverage , etc.)
• Silicon Support (Test-case creation for ATE characterisation and assisted with required debug and analysis to sign off on datasheet numbers.)

Sep 2018 – Jul 2019 · 10 mos · Gurgaon, India

• Worked on a project “ Protocol Analyzer / Jammer “ based on PCIE .

Jun 2018 – Aug 2018 · 2 mos · Gurgaon, India

• Worked on GPS using STM32 micro controller in “Data and Radio Systems” team .