May 2011 – May 2014 · 3 yrs

Feb 2010 – Apr 2011 · 1 yr 2 mos

Aug 2006 – Feb 2010 · 3 yrs 6 mos

• Description: Worked as physical design lead for a complex network switching chip
• Worked as physical design lead which involved top integration, planning, budgeting for the hierarchical blocks, power and IO ring planning etc., Coordinated the whole effort with all the block owners
• Managed the team for this project which included people as well as project management.
• Owned implementation of several blocks in the 24port/48port Gigabit switch designs
• Hired and mentored new people in the team
• Handled vendor interaction, vendor trainings at Broadcom India level

Nov 2005 – Aug 2006 · 9 mos

• Description: Worked on flow and implementation of processor blocks with operating frequency of 600Mhz to 1Ghz
• Came up with a flow for place and route of the various blocks in the processor. This flow was used as an unified flow for all the blocks by all the physical design engineers in this group.
• Worked on timing correlation between Magma and PT
• Worked on implementation of a system block of the processor by combining all the synthesizable components in to one block. Worked extensively on floorplanning, pin placements and structured placement for the TLB's as part of this implementation. Also handled the power routing, P&R, clock implementation, timing closure, backend verification for reliability and signal integrity and finally design rule checks. Involves working with the US counterpart teams to align and handle physical constraints for this block with respect to the custom blocks which were done there.

Oct 2003 – Nov 2005 · 2 yrs 1 mo

• Workeding as a lead physical design engineer for ASIC designs and manageding the execution across the team members.
• Description: Worked as Physical Design Engineer for TI ASIC Customer Designs -
• Responsible for IO ring creation for ASIC designs. Have experience in planning the periphery of the chip and also in creating the IO ring for flipchip and wirebond designs. Includes interactions with the packaging team, customer design center lead, customer. Acted as a center point contact for all these people to come up with the package details for every design. Owned the coordination between all the teams involved to come up with a solution for packaging ASIC designs.
• Responsible for timing closure for certain testchips which are done by the team. Includes the process from netlist till handoff to the mask shop - which involves partioning, floorplanning, budgeting, IO ring creation, timing closure, backend verification, design rule check, and signoff and release to the mask shop with all the details. Involves leading the team for three testchips consisting of contractors, new members and the customer, mentoring the team members and project management for three designs done parellely. This testchip is the first design in the 65nm node and hence involved enormous efforts to deal with the complexity of the design/library/tools used in the flow.

Sep 2001 – Sep 2003 · 2 yrs

• Worked as a product lead to develop and deploy solution for crosstalk noise analysis in the TI chip create flow
• Lead a team of 4 people to evaluate the CeltIC tool from cadence, come up with the methodology to plug in to the TI ASIC chip create flow. Involved talking to the key stake holders and to gather requirements and to align on the methodology to implement in the ASIC flow.
• Handled project management, which included projects planning, tracking, risk management, resource allocation, and requirement alignments with customers and execution. Managed support for the crosstalk noise flow for world wide TI customers
• Worked closely with EDA vendors to integrate the EDA tools in the TI ASIC flow.
• Lead the team to come up with a strategy for hierarchical noise analysis in the ASIC designs. The team came up with innovative guidelines to ensure a safe hierarchical sign-off considering all aspects of signal integrity and timing. These guidelines are used by TI customers world wide to sign -off a hierarchical design. The team also developed a checker based on the above guidelines. This checker is being used in the TI chip create flow.
• Part of the cross-functional team to come up with the strategy and implementation details to handle power management design which were widely used by the Wireless design centers across the whole of TI.
• Came up with a methodology to prune the false violations reported by Crosstalk Noise Analysis tool CeltIC. The team implemented this methodology which removes the pessimism by using timing information for propagation and critical window based violation flagging. Co-authored a paper on this methodology and this has been accepted in VLSI design conference 2003
• Lead the team to come up with a methodology for multiple modes crosstalk noise closure.
• Have given conducted many training classes for the customers world wide who are using the TI Chip create flow for noise analysis and closure

Jan 2000 – Sep 2001 · 1 yr 8 mos

• Worked as a technical lead to come up with an standard cell library architecture for libraries in each TI technology nodes
• Came up with the height/power bus architecture and metal pitch for each library after extensive analysis and comparisons. Came up with the mosfet size, nwell position etc., to get optimal performace, area and power. The library developed with an architecture developed for the 120nm node is the fastest library among the competitors.
• Worked with the Fabrication teams to come up with the transistor parameters for the various 120nm nodes based on the electrical and the layout aspect of the library.
• Did analysis to come up with strategies for fixing antenna violations at chip level
• Owned the compatability check rules script for each library.
• Studied the need for double height cells/MET2 power bus architectures etc., and presented the recommendations to the team which is being implemented in the recent technology nodes.
• Responsible for the layout audits for the whole library. Came up with the list of recommendations/checklist to be followed by the layout engineers before releasing the layouts to the customers

Jul 1995 – Jan 2000 · 4 yrs 6 mos

• Worked as a Design Engineer to develop automated solutions to develop the library cell layouts