S

Sravanthi Pedireddi

CTO

Bengaluru, Karnataka, India8 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in leading complex SoC design projects.
  • Proficient in utilizing advanced EDA tools.
  • Strong collaboration with cross-functional teams.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC and ASIC development.

Contact

LinkedIn

Skills

Core Skills

Soc DesignAsic Design

Other Skills

System-on-Chip (SoC) designEDA toolsVery-Large-Scale Integration (VLSI)physical designStatic Timing Analysislinux

Experience

8 yrs 4 mos
Total Experience
2 yrs 6 mos
Average Tenure
4 yrs 3 mos
Current Experience

Hcl technologies

3 roles

Technical Lead

Promoted

Aug 2024 – Present · 1 yr 10 mos

Lead Engineer

Promoted

Jul 2021 – Mar 2022 · 8 mos · Bangalore Urban, Karnataka, India

Member Of Technical Staff

Aug 2018 – Jul 2021 · 2 yrs 11 mos · Bangalore Urban, Karnataka, India

Intel corporation

SoC Design Engineer

Mar 2022 – Present · 4 yrs 3 mos · Bengaluru, Karnataka, India · Hybrid

  • Leading the design of complex system-on-chip (SOC) projects, utilizing cutting-edge EDA tools and methodologies.
  • Working collaboratively with cross-functional teams to deliver high-quality ASIC designs on schedule, emphasizing innovation and excellence.
System-on-Chip (SoC) designEDA toolsASIC designSoC DesignASIC Design

Tekishub consulting services

Member Of Technical Staff

Jun 2018 – Aug 2018 · 2 mos · Bangalore Urban, Karnataka, India

Semicon technolabs pvt.ltd

Physical Design Engineer

Dec 2017 – Jun 2018 · 6 mos · Bangalore Urban, Karnataka, India

Education

Malla Reddy Institute of Technology & Sciences

Master's degree — Embedded systems & VLSI design

konaseema institute of medical sciences and engineering

Bachelor's degree — Electronics and Communications Engineering

Stackforce found 100+ more professionals with Soc Design & Asic Design

Explore similar profiles based on matching skills and experience

Baranidharan Sivapatham

Baranidharan Sivapatham

Vice President : FPGA

at Barclays

Singapore, Singapore20 yrs 10 mos exp
ASICFPGASRESoCTrading Platforms
Raghu Reddy

Raghu Reddy

Staff Engineer

at Broadcom

Bengaluru, India13 yrs 11 mos exp
Tejaswini T R

Tejaswini T R

Physical Design Engineer ( On Contract )

at MediaTek

Bengaluru, India1 yr 9 mos exp
Physical DesignStatic Timing AnalysisDigital DesignAnalog Electronics
SR

Sujaata R

Senior Member of Technical Staff

at AMD

Bengaluru, India14 yrs 11 mos exp
Chirag Kakani

Chirag Kakani

Senior Verification Engineer

at NVIDIA

Bengaluru, India9 yrs 10 mos exp
VerilogSystemVerilog
Ajinkya Kautikwar

Ajinkya Kautikwar

Applications Engineer II

at Synopsys Inc

Yavatmal, India5 yrs 1 mo exp
Pankaj Jaiswal

Pankaj Jaiswal

Platform Power and Performance Engineer

at Intel Corporation

Bengaluru, India1 yr 9 mos exp
Very-Large-Scale Integration (VLSI)CMOS
Neha Tabassum

Neha Tabassum

ASIC Design and Verification Engineer

at Avalon Holographics

India8 yrs 6 mos exp