Srisurya Konduri

VP of Engineering

Bengaluru, Karnataka, India21 yrs 10 mos experience

Highly Stable

Key Highlights

Over 23 years of experience in ASIC and ARM-based SoCs.
Expert in end-to-end chip ownership and delivery.
Strong leadership in building high-performing engineering teams.

Stackforce AI infers this person is a Semiconductor and IoT expert with extensive experience in ASIC design and ARM architecture.

Contact

Skills

Core Skills

Custom SiliconEnd‑to‑end OwnershipSoc ImplementationRtl VerificationCpu/gpu Design

Other Skills

Engineering LeadershipChip leadARM SoCDesign Netlist GenerationFPGA/Emulation PlatformsRTL IntegrationFront-End ActivitiesSubsystem IntegrationSensor ManagementSystem Verification PlanSubsystem DesignIntegrationMulti-Core ConfigurationReliability EngineeringSystem on a Chip (SoC)

About

Currently working with AMD India as Sr engineering manager • 6 years as a Senior SoC Engineer for HPG group, intel, India 12 years’ experience with ST Microelectronics, India. • 3 years’ experience as a Senior Staff Engineer for CPU/GPU implementation group. • 3 years’ experience as a Manager, Customer support for SRAM memory products. • 4 years’ experience as an IP Design Engineer developing memory/SRAMs. • 2 years’ experience as Quality Manager for the Design group. Technical Know-how includes > Working knowledge of ASIC design flow, including Front-end activities, i.e. RTL-to-Netlist, functional verification, and timing analysis using Synopsys/Cadence design tool sets. > Working knowledge of ARM v7 Cortex-A/R/M family of processors and associated peripherals. > Strong working knowledge of various aspects of design, Characterization and back-end activities in developing a variety of self-timed memories (SRAMs and ROMs) > Experience in product development, including prototyping microprocessor/CPLD based board level design, and PCB layout.

Experience

21 yrs 10 mos

Total Experience

8 yrs 7 mos

Average Tenure

4 yrs 7 mos

Current Experience

Amd

Senior Engineering Manager

Oct 2021 – Present · 4 yrs 7 mos · Bangalore Urban · On-site

Senior engineering manager and chip lead with over 23 years of experience delivering custom ASICs and ARM‑based SoCs from architecture through production silicon.
I specialize in end‑to‑end chip ownership, including SoC architecture, RTL integration, front‑end execution, DFX, and silicon readiness. I have led multiple productized chips and successfully driven A0‑to‑production delivery for complex SoCs, working closely with physical design, validation, and manufacturing teams.
I bring a hands‑on leadership style, maintaining deep technical involvement while building strong teams and ownership culture. I have built IP teams from scratch, delivering ARM‑based compute subsystems, and led large front‑end organizations (40+ engineers) across RTL integration and DFX.
Known for execution rigor, quality focus, and calm leadership through ambiguity, I am passionate about building reliable, scalable silicon platforms that ship on schedule and perform in production.

Engineering LeadershipChip leadCustom SiliconEnd‑to‑End OwnershipARM SoC

Intel corporation

Sr. SoC Designer

Apr 2016 – Oct 2021 · 5 yrs 6 mos · Bengaluru Area, India

Primary Responsibilities
> Implementation of SoC for IoT, mobile, and Client application
o Interacting closely with system architects to understand the end-user needs/use-cases
o Configure and integrate (Front-End) of various blocks build a SoC.
o Basic functional and RTL verification for the integrated block/sub-system configuration.
o Generate design netlist and follow through with the Back-End team for physical implementation.
o Participate in platform level activities including FPGA/Emulation platforms.
> Impart training on the SoC development methodologies used in the group.
Delivered projects
> SoC RTL Integration for mobile application.
o Responsible for all RTL integrated, including RTL sanity and other Front-end activities.
o Single point of contact to represent RTL team for platform activities, including pre and post-silicon activities during product life-cycle.
> Responsible for integration of Atom-based sub-system for IoT application.
o Subsystem is for controlling/managing sensors and communication IPs connected to SoC.
o The subsystem also included TSN IPs and Timed GPIOs that require definitive time response.

SoC ImplementationRTL VerificationDesign Netlist GenerationFPGA/Emulation Platforms

Stmicroelectronics

4 roles

Senior Staff Engineer

Promoted

Jun 2013 – Mar 2016 · 2 yrs 9 mos

o Primary Responsibilities
> Design and implementation of CPU/GPU Subsystems
>>Interacting closely with customers to understand their needs and offer appropriate solutions that maximizes performance and minimizes overall costs.
>>Configure and integrate (Front-End) of core block, along with desired peripheral blocks.
>>Basic functional and RTL verification for the sub-system configuration. Define in-depth system verification plan.
>>Generate design netlist and follow through with the Back-End team for physical implementation.
>>Support the customer for integration of core/sub-system with the SOC, macro verification with SOC components and post silicon debug.
o Delivered projects
> Design and implementation of ARM Cortex-R4 based subsystem for controller block in a Optical network switch.
> Design and implementation of ARM Cortex-A7 based subsystem for industrial application.
>>Multi-core configuration with high stress on product reliability.
> Design and implementation of ARM Cortex-M0 based subsystem for automotive application.
>>Multi-Core Subsystem to interact and control a number of external components.
> Design and implementation of ARM Cortex-R4 based Subsystem for Image sensor.
> Design and implementation of ARM Cortex-A7 based subsystem for gaming application.

CPU/GPU DesignRTL VerificationSystem Verification Plan

CRM

Apr 2010 – Jul 2013 · 3 yrs 3 mos

Responsibilities
To support internal and external customer of SRAM memory products.
o Interact closely with customers to understand their needs and offer appropriate cost effective solutions, either from internally developed offer or an acquired third party solutions.
o Maintain knowledge database for customers, simplifying the usage of the offered products.
To enable maintain competitive edge
o Enable product feature enhancements based on customer feedbacks.
o Track Competitor’s products for feature/performance comparison and benchmarking

Technical Leader

Promoted

Aug 2006 – Mar 2010 · 3 yrs 7 mos

o Primary Responsibilities
Formulating design specifications after discussions with customer.
Designing memory products based on specific Customer needs.
Maintaining the complete range of memory products on continual bases, based on customer feedbacks.
Resolving Technical issues by participating in cross-functional and multi-site teams at various stages of design and production.

Design Engineer/Quality Manager

May 2004 – Aug 2006 · 2 yrs 3 mos

o Primary responsibilities
Maintaining the various Process Flows and ensuring that the design teams adhere to the defined flows and industry standards.
Ensure the Quality of Customer Deliverables and facilitate timely resolution of customer returns
Create and track Quality indices to provide a snapshot of group’s quality health.