sundeep babbala — Software Engineer
Expertise in RTL to GDS: 1) Synthesis of High performance Data-path 2) Floorplan, Placement, Routing & Signoff (Timing and quality across technology nodes) 3) Clock Tree Synthesis 4) DFT Network Delivery to all the clusters/blocks/sub-systems of the micro-processor Core 5) High Speed Noise Congergence fo Clusters/Blocks 6) Low Power Methodologies 7) Physical Verification (DRC/LVS/ERC/Antenna @ Block level) 8) Dynamic Design expertise (Multimode Multicorner with wide voltage range) ASIC Pre-Si Verification Engineer: 1) Expertise in owning Bus protocol 2) Languages: System Verilog, Verilog, Specman, Perl, Shell 3) Expertise in creating functional verification infrastructure and test bench 4) Creation of multiple cycles of test-plan to sign-off for block and sub-system environment
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 8 mos
Skills
- Functional Verification
- System Verilog
Career Highlights
- Expertise in RTL to GDS methodologies.
- Proficient in functional verification and test bench creation.
- Strong background in low power methodologies and physical verification.
Work Experience
Intel Corporation
Soc val engineer (6 yrs 5 mos)
Qualcomm
SoC verification engineer (1 yr 3 mos)
Intel Corporation
Internship (1 yr)
Internship (1 yr)
Education
Master’s Degree at VIT UNIVERSITY
Bachelor’s Degree at pridarshini college of engineering
