Tejaswini Holla K

Product Engineer

Karnataka, India8 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in SoC emulation and reset verification.
  • Strong background in VLSI design.
  • Proven ability to create effective test plans.
Stackforce AI infers this person is a VLSI design engineer with expertise in SoC verification and emulation.

Contact

LinkedIn

Skills

Core Skills

Reset VerificationEmulationPatch Verification

Other Skills

Test plan creationDebuggingFirmware interactionMicrosoft OfficeMicrosoft WordMicrosoft PowerPointCLeadershipC++C (Programming Language)Verilog HDLProject ManagementEmbedded SystemsVery-Large-Scale Integration (VLSI)Digital Electronics

About

Working in SoC Emulation based reset verification for DATA center CPU. Interested in the field of VLSI design.

Experience

8 yrs 9 mos
Total Experience
6 yrs 9 mos
Average Tenure
8 yrs 9 mos
Current Experience

Intel corporation

2 roles

SoC Design Verification Engineer

Aug 2022 – Present · 3 yrs 9 mos

  • reset verification using emulation
  • Test plan creation for reset domain
  • interacting with different firmware flows
  • debugging errors found
  • interacting with different domains for cross products
Reset verificationEmulationTest plan creationDebuggingFirmware interaction

Intern

Aug 2021 – Aug 2022 · 1 yr

Patch VerificationEmulation

Photonics r&d center

Research Intern

Jan 2020 – Feb 2020 · 1 mo · The Oxford College of Engineering, Bangalore

Fiabilite network solutions private limited

Full stack IOT Development Intern

Jul 2019 – Aug 2019 · 1 mo · Mangaluru, Karnataka, India

  • Full stack IOT intern

Ieee

Member

Aug 2017 – Present · 8 yrs 9 mos

Education

Manipal School of Information Sciences

Master of Engineering - MEng — VLSI Design

Jan 2020 – Jan 2022

Canara Engineering College

Bachelor of Engineering

Jan 2016 – Jan 2020

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