Vemanaboina Vamsi — Software Engineer
Currently I am working as Sr Engineer verification @Qualcomm Skills: Verilog, SystemVerilog, UVM, C, TCL May'26 -till Working as senior verification engineer in Turing Subsystem team at Qualcomm Jan'24 - May'26 Worked as a Senior Engineer in ASIC Digital Design at Synopsys India, I specialize in UVM Testbench development, assertion-based verification, and coverage closure for high-speed MRDIMM/RDIMM DDR5 PHYs May'22 - Apr'23 I have worked as IP LOGIC DESIGN ENGINEER as GRADUATE TECHNICAL INTERN for ONE YEAR MAY 2022-APR 2023 • In INTEL Corporation I have worked on Physical layer design and Set Reset Controller design for Intel Agilex FPGA device •Where my responsibilities are to design the modules with Verilog and TCL , TERP scripting’s and timing analysis • I have experience of Synthesis and Simulation on Quartus Tool & Xilinx Tools
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and FPGA design.
Location: Nellore, Andhra Pradesh, India
Experience: 2 yrs 4 mos
Skills
- Rtl Verification
- Universal Verification Methodology (uvm)
- Asic Digital Design
- Uvm
- Logic Design
- Digital Logic
Career Highlights
- Expert in UVM and RTL Verification methodologies.
- Strong background in ASIC Digital Design and verification.
- Hands-on experience with FPGA design and timing analysis.
Work Experience
Qualcomm
Senior Design Verification Engineer (0 mo)
Synopsys Inc
ASIC Digital Design Sr Engineer (2 yrs 4 mos)
Intel Corporation
Graduate Technical Intern (11 mos)
Education
Master of Technology - MTech at Indian Institute of Technology (Banaras Hindu University), Varanasi
btech at NBKR Institute of Science and Technology
intermediate at sri vema junior college
SSC at ZPP High School,OZILI
