Venkata Siva Reddy — Software Engineer
More than 14 years of experience in physical design methodologies through Graphic chips && PCI Express Switches .Targeted for desktop and mobile applications at 65nm,45nm and 28nm , 14nm , 7m technologies Handled complex blocks in various successful Tape-outs with Multi million gates. Experienced in floorplanning, placement and optimization for timing closure, clock network planning, power distribution planning and routing at block level. Knowledge of static timing analysis concepts for both block level and top-level. Strong knowledge in signal integrity issues such cross-talk, EM and IR drop. Working knowledge of low power methodologies and impact on overall design goals. Knowledge of post layout physical verification and DFM rules. Specialties: P&&R Tools :: SOC-FE (Cadence), Aprisa (Atoptech) ,IC- Compiler (Synopsis) , Sierra Pinnacle (Mentor Graphics) Extraction Tools :: Star-RC Timing Analysis Tools :: Primetime (PT), Encounter Timing System (ETS) Cross-Talk Analysis Tools :: PT-SI Physical Verification Tools :: Caliber(Mentor Graphics) ASIC Synthesis Tools :: DC-Compiler (Synopsis) Scripting Languages :: Perl, SED, TCL, AWK
Stackforce AI infers this person is a VLSI Design Engineer with extensive experience in physical design and timing analysis.
Location: Bengaluru, Karnataka, India
Experience: 17 yrs 3 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Over 14 years in physical design methodologies.
- Expert in static timing analysis and optimization.
- Proven track record in successful tape-outs.
Work Experience
AMD
SMTS Silicon Design Engineer (3 yrs 8 mos)
Intel Corporation
SOC Design Engineer (4 yrs 9 mos)
Broadcom Inc.
IC Design Engineer (5 yrs 6 mos)
AMD (Soctronics)
Physical Design Enginner(Full Time Consultant) (3 yrs 5 mos)
