Vijay Kumar Are

Software Engineer

India13 yrs 9 mos experience

Highly Stable

Key Highlights

12.5 years of experience in DFT engineering.
Expert in ATPG and scan insertion methodologies.
Proven track record in yield improvement and DRC analysis.

Stackforce AI infers this person is a Semiconductor DFT Engineer with extensive experience in ATPG and functional verification.

Contact

Skills

Core Skills

Functional VerificationSynopsys ToolsMentor Diagnosis ToolEmulatorAtpgYield ImprovementRtl VerificationPattern Generation

Other Skills

TestKompressXilinx ISETortoise SVNQuesta simQuesta visualizerCadence VirtuosoDRC analysisEDT logic generationLabVIEWLinuxMicrosoft OfficeCQuatus iiMicrosoft ExcelWindows

About

1. DFT Engineer with 12.5 years of experience 2. Currently working as Sr staff DFT Engineer at Qualcomm india pvt. ltd. Bangalore 3. Previously Worked with Microsemi India Pvt. Ltd, Qualcomm India Pvt. Ltd. and Xilinx Asia pacific ltd. Singapore. 8. Good knowledge on scan insertion. 9. Good Knowledge on ATPG pattern generation at block level, pattern retargeting at SOC level. 10. Good Knowledge of IEEE 1149.1, 1500 and 1687 IJTAG standards. 11. Good Knowledge on Gate level simulations of ATPG patterns at both block and chip level with and without SDFs. 12. Post-Silicon-Support on ATPG (stuck-at and at-speed). 13. MBIST generation and Simulation using Mentor, Synopsys 14. ATPG Patterns Validation on Emulator using veloce (Mentor) 15. Good understanding of BSCAN and MBIST. 16. Developed FPGA designs using Microsemi Libero, Xilinx Vivado . 17. Worked on Synopsys E16, E16x2 and C10 PHY test patterns generation at block, SOC porting and simulations. 18. Scan, Mbist through USB interface. 19. Testbench development using OVM and Verilog. 20. Ability to interpret and convey technical ideas to the team, resulting in greater compliance and co-operation. 21. Demonstrated commitment to upholding the highest standards of quality and accuracy.

Experience

13 yrs 9 mos

Total Experience

2 yrs 5 mos

Average Tenure

1 yr 5 mos

Current Experience

Qualcomm

Sr staff

Dec 2024 – Present · 1 yr 5 mos · India · On-site

Maxlinear

Staff dft engineer

Jun 2022 – Oct 2024 · 2 yrs 4 mos · Singapore, Singapore

Mentor diagnosis toolFunctional VerificationSynopsys toolsTestKompress

Xilinx

Senior DFT Engineer

Sep 2018 – Jun 2022 · 3 yrs 9 mos · Singapore

Mentor diagnosis toolFunctional VerificationXilinx ISESynopsys toolsTestKompress

Microsemi corporation

Senior Engineer DFT

Aug 2017 – Sep 2018 · 1 yr 1 mo · Hyderabad Area, India

Tortoise SVNQuesta simQuesta visualizerMentor diagnosis toolFunctional VerificationEmulator+2

Qualcomm

Senior Engineer

Sep 2016 – Aug 2017 · 11 mos

Mentor diagnosis toolEmulatorTestKompress

Microsemi corporation

2 roles

DFT Engineer - II

Aug 2012 – Aug 2016 · 4 yrs

Project1: Next generation SOC FPGA’s
Worked on the ATPG with and without on-chip compression
Worked on the DRC and coverage analysis to address DRC issues and meet coverage goals
Worked on the timing and no timing simulations of ATPG patterns at chip level and block level
Instrumental in bringing up DFT testcases at wafer level and package level on first silicon
Debugged key yield loss issues and helped in yield improvement
Developing strategies to test ASIC/FPGA interface faults and bringing them up on silicon
Created Fabric designs which are used to test ASIC, Fabric interface and was instrumental in bringing up these testcases on silicon
Project2: Radiation tolerant FPGA’s
Worked on the ATPG with and without on-chip compression
Worked on the DRC and coverage analysis to address DRC issues and meet coverage goals
Worked on the timing and no timing simulations of ATPG
Developed wrappers for all ASIC blocks to cover FPGA/ASIC interface faults.
Created Fabric designs which are used to test ASIC, Fabric interface and was instrumental in bringing up these testcases on silicon
Debugged key yield loss issues and helped in yield improvement
Project3: Next generation advanced SOC FPGA’s
Worked on the EDT logic generation and integration
Worked on the RTL verification of different DFT RTL, example WTAP
Verified MBIST logic (RTL) of one of the ASIC
Pattern generation, coverage analysis and DRC analysis for various ASIC blocks in both EDT and EDT bypass mode
Created testcases to run generated patterns in Fullchip
Created FPGA designs using Libero to test Fabric boundary scan