Krishnan Raghavan

Product Engineer

Bengaluru, Karnataka, India7 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Automatic Test Pattern Generation (ATPG) and silicon validation.
Proven track record in DFT for advanced semiconductor projects.
Hands-on experience in post-silicon debug and testing.

Stackforce AI infers this person is a Semiconductor DFT Engineer with expertise in testing and validation processes.

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Skills

Core Skills

Automatic Test Pattern Generation (atpg)Silicon ValidationSystemverilogUniversal Verification Methodology (uvm)

Other Skills

Synopsys toolsATPGDebuggingSynopsys PrimetimeMentor GraphicstessentTetramaxVerilogShell ScriptingVery-Large-Scale Integration (VLSI)CPython (Programming Language)amba apbAMBA AHBPCIe

About

Experienced DFT Engineer with a proven track record in the semiconductor industry. Proficient in ATPG, retargeting, post-silicon debug, and diverse aspects of the DFT domain. Extensive involvement in full-chip DFT activities from RTL to post-silicon across multiple project

Experience

7 yrs 4 mos

Total Experience

2 yrs 5 mos

Average Tenure

5 yrs 3 mos

Current Experience

Mediatek

DFT Engineer

Feb 2021 – Present · 5 yrs 3 mos · Bangalore Urban, Karnataka, India · On-site

Experienced in diverse semiconductor projects, including TV SoC and 5G-integrated smartphones
Worked across chip sizes ranging from 6nm to advanced 3nm technology nodes
Proficient in ATPG and adept at debugging DRC failures
Skilled in generating high-quality test patterns for different fault models
Conducted extensive simulation of test patterns to replicate ATE behavior and minimize silicon failures during production
Hands-on experience in post-silicon bring-up and silicon failure diagnosis
Played key roles in testing chips from design validation to silicon validation.
Worked on designs SSN architecture to reduce the tester time and to reduce test and product cost .
Working on 19 cores and 2 phases.
Additionally working on coverage improvements and training team on DFT concepts.