Gangadhar Chintala

Software Engineer

Bengaluru, Karnataka, India8 yrs 8 mos experience

Key Highlights

  • Expert in Universal Verification Methodology (UVM) and SystemVerilog.
  • Proven track record in VLSI industry as a Principal Engineer.
  • Strong background in Functional Verification and SoC design.
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in Functional Verification and System on a Chip technologies.

Contact

LinkedIn

Skills

Core Skills

Test PlanningSystem On A Chip (soc)

Other Skills

dveDebuggingVerdiSynopsys toolsFunctional VerificationPCIeUniversal Verification Methodology (UVM)system verilogVerilogFront-end DevelopmentVery-Large-Scale Integration (VLSI)JavaCascading Style Sheets (CSS)JavaScriptAngularJS

About

Experienced Design Verification Engineer with a demonstrated history of working in the VLSI industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Python, Pearl,Java and Linux. Strong engineering professional with a Bachelor of Technology - BTech focused in Electronics and Communications Engineering from RGUKT-NUZVID.

Experience

8 yrs 8 mos
Total Experience
2 yrs 9 mos
Average Tenure
4 mos
Current Experience

Sandisk

Principal Engineer

Jan 2026 – Present · 4 mos · Bengaluru, Karnataka, India · On-site

Excelmax technologies

Senior Design Verification Engineer

Mar 2023 – Dec 2025 · 2 yrs 9 mos · Bengaluru, Karnataka, India

Intel corporation

Senior SOC Design Engineer

Dec 2020 – Oct 2022 · 1 yr 10 mos · Bengaluru, Karnataka, India

Test Planningdve

Wipro limited

Design Verification Engineer

Mar 2017 – Dec 2020 · 3 yrs 9 mos · bangalore

Test PlanningSystem on a Chip (SoC)

Education

RGUKT-NUZVID

Bachelor of Technology - BTech — Electronics and Communications Engineering

Stackforce found 100+ more professionals with Test Planning & System On A Chip (soc)

Explore similar profiles based on matching skills and experience

Bala Shiva Vishwanatham

Bala Shiva Vishwanatham

ASIC Physical Design Engineer

at MediaTek

Bengaluru, India5 yrs exp
Physical DesignVery-Large-Scale Integration (VLSI)
Aditya Verma

Aditya Verma

Senior Lead Engineer

at Qualcomm

Bengaluru, India7 yrs 8 mos exp
Krishnendhu u.n

Krishnendhu u.n

Senior Design Engineer

at Cerium Systems

Bengaluru, India10 yrs 4 mos exp
FPGARTL Design
MS

Manikandan Subramanian

Principal Engineer

at NVIDIA

Bengaluru, India19 yrs 4 mos exp
Shikha Shrivastava

Shikha Shrivastava

SoC Design Engineer

at Intel Corporation

Hyderabad, India6 yrs 10 mos exp
Automatic Test Pattern Generation (ATPG)Scan Insertion
Amandeep Singh

Amandeep Singh

Accumulated Expertise

at Career-Wide Experience

Roorkee, India0 mo exp
Shubhankar Das

Shubhankar Das

Lead Engineer

at Qualcomm

Faridabad, India10 yrs 2 mos exp
Devank Aeron

Devank Aeron

Design Verification Trainee

at Silicon Patterns

West Delhi, India3 yrs 11 mos exp
Functional VerificationVerification and Validation (V&V)