Vishal Khetan

Software Engineer

Bengaluru, Karnataka, India7 yrs 5 mos experience

Highly Stable

Key Highlights

Expertise in Physical Design and ASIC methodologies.
Strong foundation in VLSI Design with advanced degrees.
Proficient in multiple programming languages and design tools.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and ASIC methodologies.

Contact

Skills

Core Skills

Static Timing AnalysisSynthesisDesign AutomationPhysical Design

Other Skills

SoC level constraints developmentLECSoC timing closureFlow implementationDesign implementationSupport for 7nm, 10nm, and 14nm projectsFloor & Power planningPlacementClock Tree SynthesisRoutingIR Drop measurementVerilogMatlabBasic Knowledge of C & C++Linux

About

A fully dedicated Physical Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in basic programming languages like Perl and TCL and Good knowledge of ASIC design and have one year experience as a trainee at Incise Infotech Pvt. Ltd. as Design Engineer, currently pursuing m.tech in stream of VLSI Design from Vellore institute of technology, Vellore. Strong engineering professional with Master of Technology in VLSI DESIGN from Vellore Institute of Technology, Vellore and Bachelor of Technology focused in Electronics and Communications Engineering from B. K. Birla Institute of Engineering & Technology, Pilani.

Experience

7 yrs 5 mos

Total Experience

2 yrs

Average Tenure

1 yr 3 mos

Current Experience

Qualcomm

Senior Engineer

Mar 2025 – Present · 1 yr 3 mos · India

Texas instruments

PD STA Engineer

Nov 2022 – Feb 2025 · 2 yrs 3 mos · Bengaluru, Karnataka, India

Worked on Synthesis and STA, owned SoC level constraints development and its validation, LEC and SoC timing closure.

SynthesisStatic Timing AnalysisSoC level constraints developmentLECSoC timing closure

Intel corporation

3 roles

System-on-Chip Design Engineer

Nov 2021 – Nov 2022 · 1 yr

Digital Design Engineer

Sep 2020 – Jan 2022 · 1 yr 4 mos

Design Automation Intern

Aug 2019 – Jun 2020 · 10 mos · Hyderabad Area, India

working on flow and design implementation related issues. supporting 7nm, 10nm and 14nm projects.

Flow implementationDesign implementationSupport for 7nm, 10nm, and 14nm projectsDesign Automation

Incise infotech private limited

Physical Designer

Jun 2017 – May 2018 · 11 mos · Pilani

Designing and verifying activities which includes Floor & Power planning, Placement, CTS, Routing, IR Drop measurement, STA.

Floor & Power planningPlacementClock Tree SynthesisRoutingIR Drop measurementStatic Timing Analysis+1

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI Design

Jan 2018 – Jan 2020

B K Birla Institute of Engineering & Technology, Pilani

Bachelor of Technology — Electronics and Communications Engineering

Jan 2014 – Jan 2018

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