Yogesh Jain — Product Manager

A self-motivated team player interested in learning & working on challenging protocols. I am ready to associate with an organization which progresses dynamically and give me a chance to update my knowledge and enhance my skills. EXPERIENCE Experience in RTL designing and debugging. Experience in Logic-level optimization, Resource utilization and Timing closures. Experience of working on UART, USB, Ethernet, Bluetooth, AXI, I2C, SPI, MIL-1553B, JESD204B communication protocols. Experience of working on interfaces like High speed ADC, LMX/LMK(on-board PLL), Temperature Sensor, SPI Flash, P-NOR Flash, EEPROM, SRAM, CAMLINK, DDR2, DDR3. SKILLS Programming Languages: VHDL, Verilog, TCL Scripting Tolls Used: ISE, PlanAhead, Vivado(Xilinx), Libero SoC(Microsemi), Quartus Prime Wave Analyzing Tools(Debuging Tools) : ISE, Modelsim, Chipsope-Pro, SmartDebug, Oscilloscope Worked on FPGA: Virtex-5, Kintex-7, PROASIC3, PROASIC3E, POLARFIRE, MAX10

Stackforce AI infers this person is a proficient FPGA design engineer with expertise in communication protocols.

Location: Gurugram, Haryana, India

Experience: 2 yrs 11 mos