Rohit Thakur

Software Engineer

Faridabad, Haryana, India8 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Specialized in Cadence Perspec system verifier tool.
4 years of experience in software validation.
Proficient in multiple programming languages including C++ and Python.

Stackforce AI infers this person is a VLSI Software Validation Engineer with expertise in verification tools.

Contact

Skills

Core Skills

System VerilogPssVerilogLinux Os

Other Skills

Adobe PhotoshopC (Programming Language)C++Cadence Schematic CaptureCadence SpectreCadence VirtuosoCadence Virtuoso Layout EditorCascading Style Sheets (CSS)Digital ElectronicsHTML5Intel 8085MakefileMicrosoft PowerPointPerlPublic Speaking

About

As a Software Validation Engineer within the System Verification Group at Cadence Design Systems, I specialize in the Cadence Perspec system verifier tool. Experience: 4 years Skills: * Languages: C++, Python, Verilog, PSS, SystemVerilog (SLN), Assertion-Based Verification * Concepts: Data Structures, Static Time Analysis, Linux OS, Digital Logic Design * Protocols: UART, I2C, AXI, AHB (AMBA) * Tools & Services: Cadence Perspec, Xcelium, Jasper Gold, Jenkins, Verisium manager, Code miner Contact: rohitnaththakur1999@gmail.com or via LinkedIn.

Experience

Cadence design systems

4 roles

Software Validation Engineer 2

Promoted

Jun 2024 – Present · 1 yr 9 mos

Now working as senior software validation engineer for Cadence Perspec system verifier and Perspec Libraries

PssSLNSystem VerilogPSS

Product Validation Engineer 1

May 2022 – May 2024 · 2 yrs

Working as a PV Engineer for system Verifier tool i.e. Perspec

VerilogPssSystem VerilogC++

Product Validation Intern

Jun 2021 – May 2022 · 11 mos

Worked on Cadence Virtuoso RF flows and functionality (Advanced Nodes design ) EXL
Responsible for Testcase Regression Review , Creation, Debugging and Automation .
Worked on Stacked Die design , having multiple dies , flows for translator , Allegro to virtuoso , stream in stream out flow for generation of final GDSII files.
Worked on Codesign flow in virtuoso RF .
Also worked on Bond Wire flows that is used in Package designing. which includes creation for bond wire , bond guide , fingers etc.
Have a good working experience with Linux OS and Makefile .

Product validation trainee

Apr 2021 – May 2021 · 1 mo

Chegg india

Subject Matter Expert

Feb 2021 – Feb 2022 · 1 yr

J.c. bose university of science and technology, ymca

Committee Member at TP Office

Oct 2020 – Oct 2021 · 1 yr

International mun

Campus Ambassador Intern

Aug 2020 – Nov 2020 · 3 mos

Ieee ymca sb

4 roles

Chairperson

Jul 2020 – May 2021 · 10 mos

After about an year of my dedicated work as Vice chair for IEEE YMCA SB I was appointed as Chairperson on 7 July 2020. Thanks to all the past Execom Members for appointing me.

Deputy chair

May 2019 – Jul 2020 · 1 yr 2 mos

In month of may 2019 I was Honoured to take the position as Vice chair person In SB of my university it was all due to my seniors guidance and my continious work for Student Branch.

Head Of Social Media Relations

Mar 2018 – Mar 2019 · 1 yr

Member

Oct 2017 – May 2019 · 1 yr 7 mos

I got selected in IEEE student branch of my university . Thanks to the seniors for selecting me. After three rounds of selection process.

Ieee delhi section student network

Industry Relation Administrator

May 2020 – Jul 2021 · 1 yr 2 mos · Delhi, India

After 1 year of Vice Chair at my SB i applied for the student network group of IEEE Delhi section. its was 2 rounds of selection procedure in which first we have to fill a questionnaire after which students were shot listed after then there was a interview round taken by previous head/mentor of the network. I passed those round from among 140 students nominations across North India .

3st technologies

Design Verification Intern

Jun 2019 – Jul 2019 · 1 mo · Noida, Uttar Pradesh, India

I spended my summer in 3st technologies and gained a lot confidence in VLSI front end design . Our mentor taught us About digital electronics started from the basics to advanced along with the Verilog HDL language used for RTL design . we also learned About STA (Static Time Analysis) used in digital circuits. After this learning part we also done coding in verilog and made 2 projects . In last week we learned about the use of linux os in VlSI industry and also about shell scripting in linux.