Abhishek Agrawal

CEO

Bengaluru, Karnataka, India7 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL design and implementation for ARM CPU sub-systems.
Proven track record with no silicon bugs across multiple tape-outs.
Strong foundation in high-speed data converter design and verification.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with a focus on RTL design and FPGA solutions.

Contact

Skills

Core Skills

Rtl DesignComputer ArchitectureVerification EngineeringFpga Design

Other Skills

ArduinoCCascading Style Sheets (CSS)CommunicationDigital Circuit DesignEmulationField-Programmable Gate Arrays (FPGA)HTMLHigh-Speed Data ConvertersLink-layer protocolsProgramming LanguagesPythonRTL CodingSystemVerilogTeamwork

About

Working along with Architects to define specifications and micro-architecture of ARM CPU sub-system followed by RTL Implementation to meet performance, area and power targets. Previously, worked on implementation of high-speed network IPs at Texas Instruments

Experience

Google

CPU Design Engineer

May 2021 – Present · 4 yrs 10 mos · Bengaluru, Karnataka, India

Working on CPU sub-system IPs including ARM cores, caches, coherent interconnect, clock manager

RTL DesignRTL CodingVerilogSystemVerilogComputer Architecture

Texas instruments

2 roles

Digital Design Engineer

Jul 2019 – May 2021 · 1 yr 10 mos · Bengaluru, Karnataka, India

RTL Designer and Verification Engineer in High Speed Data Convertors involving link-layer protocols from IEEE 802.3 standard
Worked on 3 tape-outs, with no silicon bugs till date, while gaining understanding of entire ASIC Design flow including logic synthesis, timing analysis, FPGA Emulation and Lab Debug

RTL DesignVerification EngineeringHigh-Speed Data ConvertersLink-layer protocols