Rachana Pai

Software Engineer

Mangaluru, Karnataka, India2 yrs 2 mos experience

Most Likely To Switch

Key Highlights

Expert in UVM and System Verilog for design verification.
Hands-on experience in formal verification and RTL generation.
Currently pursuing a Master's in Microelectronics and VLSI Technology.

Stackforce AI infers this person is a Microelectronics Engineer with a focus on design verification and automation.

Contact

Skills

Core Skills

Formal VerificationRtl DesignUvmSystem Verilog

Other Skills

C (Programming Language)C++Cadence GenusCadence Schematic CaptureCadence SoftwareCadence VirtuosoCadence Virtuoso Layout EditorCadence XceliumCleWinCode CoverageDigital Signal ProcessingDocument GenerationElectric softwareField-Programmable Gate Arrays (FPGA)Floorplan

About

Worked as Associate Engineer at Tech Mahindra Cerium Pvt Ltd in Design Verification domain. Expertise in UVM, System Verilog and Verilog. Currently pursuing my Masters in Microelectronics and VLSI Technology at Manipal School of Information Science, Manipal. Completed Internship in Design Automation as a part of Masters at Infineon Technologies. Currently working on automating SVA for formal Verification in Design Automation team at Infineon Technologies.

Experience

Infineon technologies

2 roles

Design Engineer

Jun 2025 – Present · 9 mos

Apprentice

Jul 2024 – May 2025 · 10 mos

Worked on IP Standardization which consisted of RTL Generation, Property Generation(SVA), Formal Verification using JasperGold/OneSpin, Software Testing, Hardware Regression Testing and Document Generation using in-house tools.

RTL GenerationProperty Generation (SVA)Formal VerificationSoftware TestingHardware Regression TestingDocument Generation+1