Sumit Kumar — Director of Engineering
Senior Engineering Manager - SOC and IP Design Verification Manager • Good experience in ASIC/SoC and IP Design Verification in System Verilog and OVM, UVM Methodology. • Expertise in HDL & HVL languages such as Verilog, Vhdl , System Verilog and OVM , UVM Verification environments. • Leading the Design Verification for SOC’s project which includes SOC end to end design formal and functional verification. • Owning the entire design verification flow all test suits and over all metrics(code coverage ,functional coverage) on functional verifications • Cross-Functional Collaboration & Resource Management: Efficiently allocated team resources, balancing priorities and ensuring project deliverables • Mentoring Helping and guiding junior engineers /team members in technical and other flow improvements. . Expertise in building components from scratch , Knowledge of Digital design, Intel Microcontroller, ARM Cortex R5 Subsystem, Knowledge of protocols - PCI Express , AMBA- APB, AHB & AXI , MDIO and Scripting language Perl. • Experience in Functional verification, Coding Sequences & test cases, Checkers, Functional coverage, RAL & Directed and Random Stimulus based Verification , formal verifications. • Willingness to learn New technology and can adopt a new environment and culture. • A Versatile Team Player with Good Communication and Problem Solving Skills. • Self-Starter, Self-Motivated & Quick Learner . SKILL SET: Hardware Design Languages (HDL) : Verilog , VHDL Hardware Verification Languages (HVL) : System Verilog for Verification. Verification Methodologies : OVM, UVM Verification Essentials : Verification Architecture , Code coverage,Functional Coverage Tools, Formal tools Software Languages : C, C++ Operating systems : Linux, Windows XP,vista,7 Tools worked on : Xcelium, VCS, Modelsim ,INTEL Tools, Questa sim, NCSim
Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in ASIC and SoC design.
Location: Bengaluru, Karnataka, India
Experience: 14 yrs 8 mos
Skills
- Engineering Management
- Functional Verification
- Soc
- Asic
Career Highlights
- Expert in ASIC/SoC and IP Design Verification.
- Proficient in System Verilog and UVM methodologies.
- Strong leadership in cross-functional team management.
Work Experience
https://vlsid.org/committee/
Panel Chair (6 mos)
Analog Devices
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Senior Engineering Manager (3 yrs 5 mos)
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Principal Design Verification Engineer (4 yrs 8 mos)
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R&D Engineer at Broadcom limited (3 yrs 1 mo)
HCL Technologies
Member of Technical Staff (1 yr 2 mos)
Wipro Technologies
SOC Design Verification Engineer (2 yrs 9 mos)
Education
Executive Management at Indian Institute of Management Bangalore
Master of Technology - MTech at Birla Institute of Technology and Science, Pilani
Bachelor of Engineering - BE at Dayananda Sagar College of Engineering, BANGALORE
at DAV Public School Hazaribagh
