RamaKrishna Pothuri — CTO

Career Summary:  Proven expertise in technically leading ASIC/CPU/SOC Physical Design teams and signoff to foundry for large SoC chips with global engineering teams.  Worked on different aspects of the Physical Design including Synthesis, Floorplan, Place, CTS, Routing, STA and Timing closure, PDN, ATPG, DFX, Power, Custom Implementation, RV-IR and Physical verification  Handling both Technical Lead and Engineering manager roles, groomed next level leads  Involved in multiple Technical Forums and lead SD efficiency improvement Work groups in Division Level  3D-IC: expertise in multi - chiplet design Planning & Implementation, Shaft alignment to minimizing Die to Die latency, optimizing floorplans for 3D-IR Simulations & IP reuse, 3D Power planning and PDN convergence  Well versed with flip-chip, wire-bond design implementations, clock topologies, power distribution networks, Signal Integrity, low-power design techniques  Participated in Back-End methodology/CAD Flow development activities  Project planning, schedule preparation, resource allocation, task assignments and tracking.  Reporting to executive management the status of projects under development to give a clear picture of timelines, risks and ambiguities  Project and people management experience at Intel with a team of up to 10 people.  Involved in 16+ Tape-outs on advanced process nodes (18A / 20A / 3 / 5 / 10 / 14 / 28 /32 / 45 / 65 nm)  Involved and lead the process for Hiring critical resources and interns for Team Technical Skill Set:  Synthesis: Design Compiler & Fusion Compiler  Place and Route: Synopsys Fusion Compiler (ICCII, FC), Cadence Encounter (EDI & Innovus)  RC-Extraction: Star RC-XT  Static Timing Analysis: PT-PX, Primetime, Tango Intel proprietary tool for latch-based design (working knowledge)  Power/IR Analysis: RedHawk (Working Knowledge)  Methodology Development: • multi-Chiplet design: Foveros (3D) direct assembly, power delivery scheme and signoff MOW • Expertise in Abutted Hierarchical Physical Design methodology (Channel-less design) • Custom Routes for High-Speed Routing and channel planning for Multi VA Designs  Low Power methodologies worked on: Multi Voltage, DVFS, AVFS, Adaptive Body Biasing (Well Biasing), Power Gating (Shut Down), Gate length biasing, and multi-Vth design flows  Power Intent: UPF, CPF

Stackforce AI infers this person is a leader in semiconductor design and physical implementation for advanced technology nodes.

Location: Bengaluru, Karnataka, India

Experience: 13 yrs 4 mos