V

Vikram G.

Associate Partner

Bengaluru, Karnataka, India29 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design across multiple technology nodes.
  • Proficient in Full Chip Static Timing Analysis and Synthesis.
  • Experienced Design Manager with program management skills.
Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in VLSI and ASIC development.

Contact

Skills

Other Skills

Static Timing AnalysisPhysical DesignRTL codingTimingVLSIVerilogEDARTL designTCLFunctional VerificationSystemVerilogPhysical VerificationLogic SynthesisSystem on a Chip (SoC)Semiconductors

About

 Physical Design experience using nodes 130nm, 90nm, 65nm, 40nm, 28nm, 16nm, 10nm  Full Chip Static Timing Analysis and Synthesis  Verilog and VHDL coding for ASIC's and FPGA's  Design Manager with Program Management experience

Experience

29 yrs
Total Experience
3 yrs 2 mos
Average Tenure
7 yrs
Current Experience

Samsung r&d institute india - bangalore private limited

Associate Director

May 2019Present · 7 yrs · Bengaluru, Karnataka, India

Ust global

Associate Delivery Manager

Sep 2016May 2019 · 2 yrs 8 mos · Penang, Malaysia

Mediatek

Principal Engineer

Feb 2015Sep 2016 · 1 yr 7 mos · Bengaluru Area, India

  • Top Level Physical Design and STA

Lsi corporation

2 roles

Engineering Manager

Jan 2013Jan 2015 · 2 yrs

ASIC Design Staff Engineer

Jan 2008Jan 2013 · 5 yrs

Sasken communication technologies ltd

2 roles

Lead Engineer

Promoted

May 2005Jan 2008 · 2 yrs 8 mos

Senior Design Engineer

Mar 2001Mar 2004 · 3 yrs

Infineon technologies

Senior Design Engineer

Mar 2004Mar 2005 · 1 yr

Aerospace systems pvt ltd

Engineer

May 1998Mar 2001 · 2 yrs 10 mos

Vicap semiconductors

Design Engineer

Jan 1997Apr 1998 · 1 yr 3 mos

Education

Indian Institute of Technology Jodhpur

Doctor of Philosophy - PhD — Electrical and Electronics Engineering

Jan 2023Present

Coventry University

MSc — MSc in VLSI System Design

Jan 2004Jan 2008

Karnatak University

Bachelor of Engineering — Electronics and Communication

Jan 1992Jan 1996

JSS College of Science

PUC — Science

Jan 1990Jan 1992

K E Boards High School

SSLC — 10th Standard

Jan 1990Jan 1992

Stackforce found 100+ more professionals with Static Timing Analysis & Physical Design

Explore similar profiles based on matching skills and experience