Shivangi Dixit

Software Engineer

Boston, Massachusetts, United States4 yrs 2 mos experience

Highly Stable

Key Highlights

Over 4 years of experience in Electronic Design Automation.
Proficient in C/C++ with strong analytical skills.
Specialized in Intelligent Systems and Information Security.

Stackforce AI infers this person is a Software Engineer specializing in Electronic Design Automation and Intelligent Systems.

Contact

Skills

Core Skills

C++Power AnalysisRtl DesignFpga Synthesis

Other Skills

Algorithm AnalysisAlgorithm DesignAlgorithmsApache HadoopCCascading Style Sheets (CSS)Data StructuresEthical HackingGDBGoogle ColabHTML5ICC2Information Security ManagementJavaScriptLinux

About

Currently working as a Software Engineer II at Cadence Design Systems, leveraging a strong foundation in Electronic Design Automation (EDA) and expanding into broader software engineering responsibilities. I hold an M.S. in Computer and Information Sciences from the University of Texas at Arlington, specializing in Intelligent Systems, and a prior M.Tech in Information Security from India. I bring over 4 years of experience as an R&D Engineer II in the EDA domain, having worked with industry leaders Synopsys and Mentor Graphics (now Siemens EDA). I am proficient in C/C++ and possess strong analytical and problem-solving skills. My work has spanned FPGA synthesis tools such as Xilinx Vivado and Mentor Precision RTL, as well as power analysis tools including ICC2, Fusion Compiler, and PrimeTime PX.

Experience

Cadence

Software Engineer II

Aug 2025 – Present · 7 mos · Burlington, Massachusetts, United States

Synopsys inc

2 roles

R&D Engineer II

Promoted

Aug 2021 – Mar 2023 · 1 yr 7 mos · Noida, Uttar Pradesh, India

R&D Engineer I

Aug 2019 – Aug 2021 · 2 yrs · Noida, Uttar Pradesh, India

Worked as part of the Power Analysis module of Fusion Compiler (FC)
Tech stack: C++, Verilog, Linux, TCL, GDB, Perforce (GUI and command-line), Valgrind and coverity fixes

C++VerilogLinuxTCLGDBPerforce+2

Mentor graphics

Software R&D Intern

Jan 2019 – Aug 2019 · 7 mos · Noida, Uttar Pradesh, India

Worked as part of RTL Precision Synthesis team. Designed an automated mechanism to extract conditional timing models in FPGAs using Perl scripting language and Verilog (HDL) to create various instantiated testcases. Mapped different multiplier testbench to DSP blocks and analyzed the generated timing reports.
Tech stack: Verilog, C, TCL, Perl scripting language

VerilogCTCLPerlRTL DesignFPGA Synthesis

Indira gandhi delhi technical university for women

Teaching Assistant

Oct 2018 – Dec 2018 · 2 mos · Delhi, India

Mentored sophomore students in Information Security Research Lab along with implementing curriculum based lessons.
Tech stack: Apache Hadoop

Apache Hadoop

Iiit hyderabad

Summer Student

Jun 2018 – Jul 2018 · 1 mo · Hyderabad, Telangana, India

Understanding applications and challenges of Social Network Analysis by visualizing Twitter data, learning about security and privacy in Online Social Media. Learnt techniques to use Natural Language Processing (NLP) and Sentiment Analysis for feature extraction and representation of collected data.
Tech stack: Python, Google Colab

PythonGoogle Colab