Himanshu Bhatiani

Product Manager

New Delhi, Delhi, India7 yrs 9 mos experience

Key Highlights

6 years of experience in semiconductor industry.
Expert in ASIC/FPGA verification methodologies.
Proven track record in leading complex verification projects.

Stackforce AI infers this person is a semiconductor verification engineer with expertise in ASIC and FPGA methodologies.

Contact

Skills

Core Skills

Asic/fpga VerificationUvmFunctional VerificationXcelium

Other Skills

AHBAMBAAPBAXIAXI3AXI4Bug reportingCC++CMOSDebuggingDigital ElectronicsEDAEngineeringField-Programmable Gate Arrays (FPGA)

About

Highly accomplished and results-driven Staff Verification Engineer with 6 years of experience in the semiconductor industry. Specializing in ASIC/FPGA verification, I have a deep understanding of industry-standard methodologies such as UVM and SystemVerilog. Throughout my career, I have successfully led and executed verification projects for complex IP's and SoC designs, ensuring functional excellence and meeting project timelines.

Experience

Synopsys inc

Staff ASIC Design Verification Engineer

May 2024 – Present · 1 yr 10 mos · Noida, Uttar Pradesh, India

Microchip technology inc.

2 roles

Senior Verification Engineer

Promoted

Sep 2022 – May 2024 · 1 yr 8 mos

Develop verification strategies and test plans for both block-level and subsystem-level verification based on design specifications and system requirements.
Design and implement block-level and subsystem-level testbenches, verification environments, and test scenarios.
Develop and execute test cases to validate the functionality, performance, and integration of blocks and subsystems.
Collaborate closely with cross-functional teams to ensure proper integration and compatibility of blocks and subsystems within the larger system.
Debug and resolve issues identified during the verification process, working closely with design and integration teams.

Verification strategiesTest plansTestbenchesVerification environmentsTest scenariosTest cases+3

Verification engineer II

Jun 2021 – Sep 2022 · 1 yr 3 mos

Cadence design systems

2 roles

Verification Engineer

Aug 2019 – Jun 2021 · 1 yr 10 mos

Functional Verification of Cadence Simulator Xcelium using System Verilog, Verilog, VHDL and Scripting Languages like C Shell, Perl, and Python.
Functional spec review, defining validation test-plan, test-case creation and automation, and bug reporting for the features developed for Single-core Xcelium.
Cross-Functional testing of all the features with MSIE (Multi-Snapshot Incremental Elaboration), Low Power and coverage-driven verification before delivering the feature to the customer for better deployment.

Functional VerificationSystem VerilogVerilogVHDLScripting LanguagesTest-case creation+2