Jyoti Gulati — CTO
14 years of proven technical leadership in processor verification, system level, IP and FPGA verification. Key skills include Project Management, Hands on System Verilog UVM based environments, testbenches, testcases, functional coverage, code coverage, assertions, and RTL debugging. Rich experience of working through all serial, communication and memory protocols. Had opportunities to work with leaders in VLSI space viz. ARM, STMicroelectronics, WD, e-Asic(Intel) and Synopsys
Stackforce AI infers this person is a VLSI and ASIC verification expert with extensive leadership experience.
Location: Bengaluru, Karnataka, India
Experience: 19 yrs 2 mos
Career Highlights
- 14 years of technical leadership in processor verification.
- Expertise in System Verilog UVM based environments.
- Rich experience with VLSI leaders like ARM and Synopsys.
Work Experience
Cisco
ASIC Engineering Leader (10 mos)
ASIC Engineering Leader (10 mos)
AMD
Member Of Technical Staff (4 yrs 6 mos)
Mobiveil Inc.
Engineering Manager (2 yrs 5 mos)
Synopsys
Manager R&D (2 yrs 10 mos)
Ciena India Pvt Ltd
Module Lead (2 yrs)
ARM Embedded Technologies
Techinal Lead (1 yr 5 mos)
Senior Engineer (1 yr)
STMicroelectronics Pvt Ltd
Design Engineer (4 yrs 7 mos)
Associate Design Engineer (5 yrs)
Education
B Tech at J.C. Bose University of Science and Technology, YMCA
