kanav gupta

CEO

Gurugram, Haryana, India13 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in quantitative trading and algorithm development.
  • Proven track record in physical design execution.
  • Innovative solutions in power systems and wireless communication.
Stackforce AI infers this person is a Quantitative Trader with expertise in telecommunications and energy sectors.

Contact

Skills

Core Skills

Physical DesignChip DesignGame Theory ApplicationsAlgorithm DesignPower System EngineeringHarmonic Analysis

Other Skills

Algorithm developmentAlgorithmsAnalysisCC++Clock tree synthesisCost analysisFull chip floor planningGame theoryHarmonic currents trackingJavaMATLABMatlabMethodology developmentMicrosoft Excel

Experience

Pace stock broking services pvt. ltd.

Quantitative Trader

Nov 2023Present · 2 yrs 4 mos · Gurugram, Haryana, India · On-site

Quadeye

2 roles

Garden Leave

Aug 2022Jul 2023 · 11 mos · On-site

Quantitative Trader

Aug 2015Jul 2022 · 6 yrs 11 mos · On-site

Deutsche bank

Senior Analyst

Oct 2013Jul 2015 · 1 yr 9 mos · Mumbai Area, India

  • Assisting Traders in buying and selling Bonds/CDS for clients & take proprietary trading positions on behalf of the Bank.
  • Suggests outlook on corporate debt by performing qualitative & quantitative analysis of financial results
  • Recommends trades by historical & comparative analysis b/w prices, Zspreads, bond basis of bonds/cds
  • Provide market liquidity through market making in Sovereign/Corps fixed income; put in place hedging if appropriate.
  • Monitor market news & events and evaluate the risk and opportunities for clients and the Bank's positions and strategy.
  • Live pricing of cross currency swaps, FTD’s, CLN, Repo Trades and monitoring and validating risk & pnl of trading books.
  • Working with operational support functions facilitate and monitor the settlement process

Qualcomm inc.

Associate Engineer

Jul 2012Oct 2013 · 1 yr 3 mos · Bengaluru Area, India

  • Responsible for Physical design execution
  • Executing full chip floor planning and partitioning, physical synthesis, place and route, clock tree synthesis, power and signal integrity analysis and timing closure
  • Involves tasks in both implementation and automation of tasks for full chip physical design in addition to new methodology development and vendor tool evaluations and integration
  • Working in a dynamic team environment with aggressive schedule, chip power consumption and area targets
  • Interacted with stakeholders from Architecture, Design, synthesis, library, package, methodology, EDA vendor teams to drive area reduction initiative
Physical design executionFull chip floor planningPhysical synthesisPlace and routeClock tree synthesisPower and signal integrity analysis+5

Syracuse university

Intern: Game theory applications in wireless communication

May 2012Jul 2012 · 2 mos · Syracuse, New York Area

  • Modeled one shot & infinitely repeated games for bandwidth sharing between radios with jammer in vicinity
  • Analyzed payoff functions of all radios & jammer, devised novel algorithms using MATLAB to reach Nash Equilibrium
  • Project initiated by US Air Force, results have direct applications in Satellites and Airborne communication networks
  • Developed the spectrum sharing rules in order to optimize the achievable rate of every user in multi-user scenario
  • Reduced reaction time of radios & jammers by 18% by prescribing a best response for every situation
Game theoryMATLABAlgorithm developmentGame theory applicationsAlgorithm design

Itc limited

Summer Intern: Effects of harmonics in power system

May 2011Jul 2011 · 2 mos · Bangalore

  • Innovated the idea of tracking harmonic currents and pin pointed sources of problem in current system
  • Studied present power distribution system and analyzed all 6 parameters of power quality
  • Examined business impact, studied different mitigation measures, did cost analysis and calculated payback time
  • Reduced the cost of installation from Rs.56 Lakh (earlier used by ITC) to Rs.9 lakh and payback time for the suggested solution came out to be just 15-16 months.
  • Finalized solutions were 1/5th in cost and 10 times more effective than the solutions adopted in other ITC units
Power system analysisHarmonic currents trackingCost analysisPower system engineeringHarmonic analysis

Education

Indian Institute of Techonology Kanpur

Bachelor's degree — Electrical Engineering

Jan 2008Jan 2012

Bhavan vidhyalaya

Senior Secondary — Science and Maths

Jan 2006Jan 2008

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