Jul 2014 – Feb 2019 · 4 yrs 7 mos

• Partitioning and floor planning for the high performance L3 cache subsystem IP.
• Clock distribution for the L3 cache subsystem.
• Clock distribution of a high performance x86 processor cluster.
• Implementation lead for CPU floating point subsystem.

Jun 2012 – Jun 2014 · 2 yrs

• 1) Puma+ - Power reduction and DFM improvement of a high performance x86 processor/cache cluster at 28nm
• 2) Skybridge - Led the clock distribution effort for ARM core + cache cluster at 20nm. Worked on timing closure on some very critical paths.
• 3) Skybridge - Led the clock distribution effort for x86 processor core + cache cluster at 20nm
• 4) Defined the VT swap methodology for Skybridge and Puma+ projects. Also worked on some other power-reduction schemes.

Jan 2012 – May 2012 · 4 mos · Dallas-Fort Worth Metroplex

• Physical implementation of DSP subsystem
• 28nm Low power implementation, 600Mhz +

Jul 2011 – Sep 2011 · 2 mos · Bangalore

• Led Physical design flow developement for SOC Encounter
• QOR improvement

May 2009 – Dec 2010 · 1 yr 7 mos · Bengaluru, Karnataka, India

• Physical Design of a hierarchical design.
• Partioning and budgeting
• Flow enhancements and maintenance.

Aug 2008 – Nov 2008 · 3 mos

• Responsible for the implementation of 3 90nm blocks in talus

Feb 2008 – May 2009 · 1 yr 3 mos

• Physical design of several blocks. Was part of 2 tape outs.

Sep 2005 – Feb 2008 · 2 yrs 5 mos

• Physical design of blocks and full chip.