Veeraraju Potta

CEO

Bengaluru, Karnataka, India18 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led a 15-member team in DDR verification.
  • Expert in low power verification strategies.
  • Proven track record in silicon tape-outs.
Stackforce AI infers this person is a Semiconductor and Automotive verification expert with a focus on low power and DDR technologies.

Contact

LinkedIn

Skills

Core Skills

Ddr VerificationLow Power VerificationDdr Phy VerificationIp Verification

Other Skills

Low Power SystemsDDR protocolsVerification coverageUPF-based simulationsPower intent validationPower-aware testbench developmentSystemVerilogUVMSpecmanUSB protocolsAutomobile SoCImage processingSystem on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)Verilog

About

ā€¢ Senior Staff Engineer | ASIC Verification | DDR & System-Level DV Experienced verification leader driving successful closure of DDR subsystem DV across multiple chipsets through to silicon. Led a high-performing 15-member team, delivering robust verification strategies and execution. šŸ’” Core Expertise: LPDDR4/5/6 protocols and low-power verification Functional verification from planning to closure at module and system levels Coverage-driven, constraint-random verification methodology UVM, SystemVerilog, and C-based environment development Image processing, USB2.0/3.0, and mobile application processor IPs Bus protocols: AXI3, AHB, APB, OCP

Experience

18 yrs 8 mos
Total Experience
3 yrs 8 mos
Average Tenure
7 yrs 6 mos
Current Experience

Qualcomm

2 roles

Senior Staff Manager

Promoted

Dec 2021 ā€“ Present Ā· 4 yrs 5 mos

  • Leading DDR Memory Controller and Low Power Verification Initiatives
  • Currently leading verification efforts for DDR memory controllers (LPDDR4, LPDDR5, LPDDR6) and low power features across multiple chipsets. Managing and mentoring a team of 15 engineers, driving technical excellence and cross-functional collaboration to ensure robust verification coverage and timely delivery. Focused on building scalable verification environments, optimizing power-aware test strategies, and fostering a culture of ownership and continuous learning.
Low Power SystemsDDR VerificationLow Power Verification

Staff Engineer

Nov 2018 ā€“ Nov 2021 Ā· 3 yrs

  • Low Power Verification Lead ā€“ DDR Subsystem (Multi-Chipset Projects)
  • Led a team of 4 engineers in the low power verification of DDR subsystems across multiple chipsets.
  • Defined and executed low power verification strategies, including UPF-based simulations, power intent validation, and power-aware testbench development.
  • Collaborated cross-functionally with design, architecture, and power teams to ensure power intent alignment and early bug detection.
  • Delivered high-quality, low-power verification sign-off under aggressive schedules, contributing to successful silicon tape-outs.
Low Power Verification

Synopsys inc

Senior Verification Engineer

May 2015 ā€“ Mar 2017 Ā· 1 yr 10 mos Ā· Bengaluru Area, India

  • DDR PHY verification which supports DDR3/4 and LPDDR3/4 protocols using SV,UVM
  • Ownership of sideband and lowpower interface
  • Worked on various training modes associated with DRAM
DDR PHY Verification

Samsung electronics

Senior Design Verification Engineer

Sep 2010 ā€“ Apr 2015 Ā· 4 yrs 7 mos Ā· bangalore

  • IP verification of MIPI-DSI(Display serial interface) using specman ,e
  • Development of UFS transport layer eVC component
  • SOC verification of Samsung Exynos Series Mobile Processor Owning USB2.0,USB3.0,JPEG using UVM
  • IP verification environment for USB2.0/USB3.0 created using UVM
  • MIPI DSIM IP verification
  • eMMC verification
IP Verification

Kpit

Senior member technical staff

May 2009 ā€“ Sep 2010 Ā· 1 yr 4 mos Ā· Bengaluru Area, India

  • IP verification of SRAM controller,Watch dog timer,External interrupt capture unit using specman,e
  • Verification of Automobile SOC used for car dashboard application and other embedded controls
IP Verification

Texas instruments

Design Engineer

Dec 2005 ā€“ May 2009 Ā· 3 yrs 5 mos Ā· Bengaluru Area, India

  • IP verification of Image processing based IP's(Noise filter,Image rotation hardware block) using specman,e
  • OCP2VBUS bridge verification
  • Still Image processing (SIMCOP) subsystem verification
  • SOC verification for VOIP based architecture
IP Verification

Education

Indian Institute of Technology, Kharagpur

Master of Technology (MTech) ā€” Computer Engineering

Jan 2003 ā€“ Jan 2005

Andhra University college of engg

Bachelor of Engineering (BE) ā€” Electronics and Communications Engineering

Jan 1999 ā€“ Jan 2003

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