Satyajit Bora

Software Engineer

Golaghat, Assam, India11 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Developed three RISC-V microarchitectures for diverse applications.
Created a blind assistance system using advanced image processing.
Expert in VLSI design and FPGA verification.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in embedded systems and microarchitecture.

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Skills

Core Skills

Vlsi DesignMicroarchitectureEmbedded Systems

Other Skills

Application-Specific Integrated Circuits (ASIC)BashCCadenceCadence Virtuoso BasicsFPGAField-Programmable Gate Arrays (FPGA)Image ProcessingLaTeXMATLABMatlabMentor Graphics Pyxis & ICPerformance AnalysisPower EvaluationPython

About

I have completed my PhD from the department of EEE, IITG in VLSI. During my PhD work, we have developed three core microarchitectures based on RISC-V ISA. The cores are targeted to three different applications: low power, IoT and Security. The cores are designed in Verilog HDL and verified using various industrial tools (Synopsys, Cadence). The designs are synthesised using Synopsys DC at 40nm/65nm/90nm technology node. The layouts of the designs are implemented on Cadence Innovus and the post-layout results are estimated using Synopsys PrimeTime. The designs are also verified on multiple Xilinx FPGA Platforms. I have also worked on the development of a blind assistance system. The work was funded by Meity, Govt. of India. The prototype was implemented on a Xilinx FPGA SoC. The system applies image processing algorithms on camera images to detect object type and distance. The information is transferred to the blind person through an audio signal.

Experience

11 yrs 1 mo

Total Experience

3 yrs 8 mos

Average Tenure

4 yrs

Current Experience

Ibm

Senior Staff Engineer

May 2022 – Present · 4 yrs · Bengaluru, Karnataka, India

Intel labs

PhD intern

Nov 2016 – May 2017 · 6 mos · Bengaluru, Karnataka, India

During the project work, I explored and evaluated power, performance and area of open-source RISC-V cores. The cores, evaluated during the project work, are Shakti (E-32, C-32), PULPino, Rocket, and River.

RISC-VPower EvaluationPerformance AnalysisMicroarchitecture

Indian institute of technology, guwahati

PHD Scholar

Jul 2015 – Jan 2022 · 6 yrs 6 mos · Guwahati Area, India

The title of my PhD work is "Design and Implementation of Core Micro-Architecture Based on RISC-V ISA". During my PhD work, we have developed three core micro-architectures based on RISC-V ISA. The first core is a small low-power core that supports RV32IM of RISC-V. The second core has an extended instruction set support for DSP applications. The third core is incorporated with a dedicated hardware unit for AES encryption/decryption.
The cores are designed using Verilog HDL and verified using industry standard tools (Xilinx, Synopsys, Cadence). The designs are synthesized using Synopsys DC at 40nm/65nm/90nm technology node. The layouts of the designs are implemented on Cadence Innovus and the post-layout results are estimated using Synopsys PrimeTime.
For the design, verification and debugging of the designs, a software environment is created using python which monitors the register and memory read/write signals to verify the functionality of the designs. The designs are also verified on multiple Xilinx FPGA Platforms.

VerilogRISC-VSynopsysCadencePythonVLSI Design+1

Iit guwahati

Assistant Project Engineer

Dec 2014 – Jul 2015 · 7 mos

During this project work, a blind assistance system was developed using stereo vision algorithms. The system uses a dual-camera setup to detect and recognise objects in front and inform the blind person through audio signals. The prototype was developed on a Xilinx FPGA platform.

Stereo VisionImage ProcessingFPGAEmbedded Systems