Nitant Singh Chouhan

Software Engineer

Bengaluru, Karnataka, India12 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

8 years of VLSI industry experience.
Expert in UVM-based test benches and verification.
Multiple Division Recognition Awards at Intel.

Stackforce AI infers this person is a VLSI Verification Engineer with expertise in functional verification and architecture validation.

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Skills

Core Skills

Verification EngineeringFunctional VerificationFormal VerificationArchitecture ValidationEmbedded Systems

Other Skills

ARMARM AssemblyARM assemblyASICAlgorithmsApplication-Specific Integrated Circuits (ASIC)Assembly LanguageCC++ElectronicsFPGALinuxMatlabMicrocontrollersMicrosoft Excel

About

• 8 years of experience in the VLSI industry as a Verification Engineer/SOC Design Engineer. • Experience with UVM-based test benches (writing tests, sequences, scoreboards, monitors, drivers), writing for SOC/IP, RTL debugging with Verdi, and writing, reviewing, and executing test plans. • Highly adaptable, flexible professional who embraces teamwork by supporting and guiding new team members, but also enjoys working independently. • Received multiple Division Recognition Award -DRA in Intel.

Experience

Qualcomm

2 roles

Staff Engineer/Manager

Apr 2025 – Present · 11 mos · Bengaluru, Karnataka, India

Staff Engineer

Jun 2023 – Present · 2 yrs 9 mos · Bengaluru, Karnataka, India

Intel corporation

SoC Design Engineer

Aug 2019 – Jun 2023 · 3 yrs 10 mos · Bengaluru Area, India · Hybrid

Nvidia

Design Verification Engineer

May 2016 – Jul 2019 · 3 yrs 2 mos · Bengaluru Area, India · On-site

Worked on test-plan development and verification of Control fabric IP using UVM methodology.
Responsible for implementing monitors, checkers, scoreboard, random and directed stimuli for various components of control fabric which include Error Monitor.
Responsible for implementation of functional coverage and ensuring functional and code coverage closure of Control Fabric IP and sign-off of coverage driven verification.
Creating and reviewing design and verification documentation.
IPs and feature verified in control fabric which include, error logging, firewall and other features.
Test plan development and maintenance of Formal Verification based setups for multiple safety IPs which includes Error Correction Codes (ECC), Parity etc. using System Verilog assertions and Perl scripting.
Held multiple team-wide knowledge sharing sessions for Formal Verification basics, Control Fabric overview, random testbench architecture.
The IPs were small, but both data-bus and control-signal intensive for the formal tool. Challenges faced converging formal tool for larger data widths.

UVM methodologytest-plan developmentfunctional coverageSystem Verilog assertionsPerl scriptingVerification Engineering+1

Arm

Graduate Engineer (Architecture Validation)

Jul 2015 – May 2016 · 10 mos · Bengaluru Area, India

Working in ARMv8 Architecture validation team(AV) . Working on developing ARMv8 A profile architecture tests and maintaining tests as for specification updates. ARM assembly is used to develop test. Worked on solving partner issues related to architecture mainly on exception models, core , etc.
Our team of 3 members aim at developing test to validate the architecture core and exception suite. Solving partner issues related to architecture, providing feedback to fastmodel team in developing simulating platform.

ARM assemblyarchitecture validationexception modelsArchitecture ValidationEmbedded Systems