Oct 2020 – Jan 2023 · 2 yrs 3 mos

• Full time senior engineer with hands on experience in Verification domain. Experience in Testbench creation, Functional Verification, Assertion based Verification, Sub-system Level Verification. Regression setup, Scripting etc.

Jun 2018 – Oct 2020 · 2 yrs 4 mos

• Verification Engineer with expertise in Functional Verification, Formal verification, Low power Verification, Test Bench Architecture and development of testcases.

Mar 2018 – May 2018 · 2 mos

• The work experience included understanding design and behavior of various modules , implementing it's design in HDL , making constraint driven layered test benches as well as creating Verification architecture followed by directed as well as CRV tests to functionally verify the DUV.

Jun 2017 – Feb 2018 · 8 mos

• Skillls acquired:
• HDL: Verilog
• HVL: SystemVerilog
• Methodology: UVM
• EDA Tools: Questa, ModelSim, Xilinx ISE
• Knowledge: VLSI Flow, RTL coding, RTL Verification, Scripting, Simulation