Aug 2019 – Aug 2024 · 5 yrs · Bangalore Urban, Karnataka, India · On-site

• My role at EdgeQ can be defined as CAD flow manager for all the backend tools except IR and PV, Fullchip timing signoff methodology owner, Fullchip Constraints & Fullchip Timing Closure Owner. Developed Synthesis/LEC/CLP/PNR & STA Flow from the scratch. Drove all the blocks including subsystem and fullchip implementation and timing signoff with very limited people.

Mar 2018 – Aug 2019 · 1 yr 5 mos · Bengaluru, Karnataka, India

• 5G Converged Modem Synthesis, LEC & Timing Lead on TSMC N7
• Owned the full 5G converged Modem STA and managed a completely new team of STA Leads for subsystem level timing closure activities.
• · Closely worked with the flow team to customize the scripts for the methodology. Wrote custom scripts to ensure the methodology doesn’t break later in the flow. Brought in enhancements in the flow based on QoR.
• · Understood the supply rails, design frequency requirement across voltage cor-ners/device scaling across the voltage corners and came up with implementation strategy for each subsystem and the signoff strategy for the Fullchip.
• · Understood the design data flow, different interfaces of subsystem and helped in coming up with better floorplan and strategy for clock balancing across partitions which helped in interface timing convergence of the design within three weeks of timing ecos.

Aug 2014 – Oct 2015 · 1 yr 2 mos · Greater Bengaluru Area

• Timing Analysis for 14nm Disp IP in Intel Process
• · Improved the timing of a design closed at 2.7GHz to 3 GHz. Manual ECO involving clock tree and re-buffering in data paths were done since sizing of cells were already exploited.
• · Simultaneously worked on four projects which were in different stages of the release. Made deliverables with high quality meeting all the requirements for the concerned release.

Oct 2015 – Mar 2018 · 2 yrs 5 mos · Greater Bengaluru Area

• Synthesis & Timing Analysis for High Performance ARM CPUs on 10nm, 12ffc, 16ffc TSMC process nodes
• · As part of High Performance team, worked very effectively to meet the PPA goals.
• · Did early analysis of design for divergence to help in faster hold closure. Provided feedback on Design to Frontend team.
• · Did effective analysis of design power and provide feedbacks to implementation team and wrote custom script for Dynamic and leakage recovery.
• · Did manual setup timing closure for high frequency design by tweaks in clock paths and flops.
• · Setting up STA, Power Recovery and Timing ECO flows for others to work on.
• · As part of Global Timing Signoff team, helped on qualifying and deciding flows for Timing, Power and ECO.
• · Grooming fresher to work on STA.

Oct 2012 – Aug 2014 · 1 yr 10 mos · Greater Bengaluru Area

• Synthesis and Timing Analysis for 28 nm HPM TSMC Process
• · Did synthesis for multiple blocks and worked on area reduction and power reduction methods for improving the QOR. Wrote custom scripts to optimize unused logic in design that synthesis tool didn’t remove.
• · Wrote custom TCL scripts for fixing setup and hold, in Goldtime and Primetime.
• · Part of Synthesis & STA implementation team which taped-out a SoC with a new modem (from Renasas) within a span of six months. I owned the STA of modem.

Sep 2011 – Oct 2012 · 1 yr 1 mo · Greater Bengaluru Area

• Qualification of Hierarchical Timing Methodology in Einstimer
• · Qualified the hierarchical timing methodology. Debugged the discrepancies between hierarchical and flat timing runs due to coupling and proposed solution for issues found.
• · Wrote tcl scripts for automating the comparison between flat and hierarchical runs and assertion generation for block level runs.

Jun 2007 – Sep 2011 · 4 yrs 3 mos · Greater Bengaluru Area

• BF50x (65nm & 90nm, LP Blackfin project)
• · Held responsible for Full chip Synthesis and Timing Analysis for BF50x (Quite challenging since Blackfin is partly custom and partly RTL based design).
• · Prepared timing ECOs for fixing violations and functional ECOs for fixing the bugs found in RTL after RTL freeze.
• · Debugging gatelevel issues related to various peripherals for BF50x.
• · Power Analysis for RTL based designs using PrimeTime-PX.
• Design of Data Formatters and Controller Unit for Complex Video Processing IP
• · Creation of module specification from Technical Requirement Document. Involved in Specification Discussions with Application Engineers. Converting Specification to Mi-cro-Arch.
• · Implementation of Micro-Arch in RTL using Verilog.
• · Above micro-arch is patented (US9251553)
• · Synthesis and Timing Analysis of Complex Video Processing IP.