Jan 2015 – Jul 2016 · 1 yr 6 mos

• Technically leading the UVM based verification of L2 cache in the next generation graphics processors.
• Preparation of verification strategy, writing test plans, developing UVM verification environments, developing test suite and coverage closure. I’m also responsible for planning and estimation of resources required for the execution of the project.

May 2010 – Dec 2014 · 4 yrs 7 mos

• Defining verification strategy, development of UVM environment, and development of test suite and coverage closure of memory subsystem testbench.
• Building UVM verification environment for the pixel back end co-processor.
• Worked on RTL & netlist equivalence checking using Cadence LEC
• Architecture definition, design, synthesis & verification of pixel back end co-processor that DMAs and post-processes the data from the shading engine to the frame buffer. This involved all tasks right from gathering of requirements from product managers, chip architects and software driver teams and converting these into specifications and carrying out the RTL coding as well as testing of the block using in house verification methods.

May 2006 – Apr 2010 · 3 yrs 11 mos

• Integration of sub-blocks of graphics IP and top level parameter based testing
• Architecture definition, design, synthesis & verification of interconnect between shading/texture units and caches.

Mar 2005 – Apr 2006 · 1 yr 1 mo

Oct 2003 – Oct 2004 · 1 yr

Jan 2002 – Jan 2003 · 1 yr · Edinburgh, United Kingdom