Sep 2021 – Dec 2022 · 1 yr 3 mos · Bengaluru, Karnataka, India

• Worked on verification of cutting edge industry first die-to-die designs with
• 1. High speed PHY IP bring-up and verification: Worked on initialization, training, retraining and TB bring-up.
• 2. Subsystem 2 die TB and verification ownership for end-to-end behavior: Worked on
• a) Creating and owning a TB <-> MAC-> PHY <-> PHY <-> MAC <-> TB system for MAC-PHY clusters and realize a real 2 die like system for simulating real world like die-to-die full-duplex low-BW/high-BW/dbg/trigger traffic types
• b) Initialization of PHY IP in HW/SW flows, training and retraining among MAC-PHY in HW/SW flows.
• c) Full-Chip traffic realization using SoC TB and verification closure from die-to-die perspective.
• d) Performance measurement and metrification as benchmarks of die-to-die traffic for real world scenarios.

Jun 2020 – Aug 2021 · 1 yr 2 mos · New Delhi, Delhi, India

• Verification planning and closure expertise.
• Lead following activities, with expertise in all protocol specifications
• 1. AMBA & Proprietary protocol bus-VIPs and verification activities for leading mobile platform chip design organization. Expertise in AHB, AXI & ARM-like Proprietary Bus protocols.
• 2. I2C-I3C-SMBus VIPs and verification. Expertise in I2C-I3C-SMBUS protocols.
• 3. Lead DFI VIP development and verification for under developing specifications of HBM3 memory.
• 4. TileLink VIP solution development

Jun 2016 – May 2020 · 3 yrs 11 mos · New Delhi, Delhi, India

• Development and verification closure of
• 1. Memory VIPs (DDR4/DDR5): Verification closure of VIPs with fast evolving specifications.
• 2. I2C/I3C VIPs: Develop VIPs and close verification as per latest specification standards
• 3. Proprietary-on-chip bus VIPs

Jun 2012 – May 2016 · 3 yrs 11 mos · New Delhi, Delhi, India

• Development of following on-chip bus VIPs. Participated in exhaustive verification closure of Network on Chip, CPU-subsystem and slave IP verification using
• 1. AMBA AHB VIPs
• 2. AMBA AXI VIPs
• 3. Next generation Proprietary (for the next generation specs) VIPs

Sep 2011 – May 2012 · 8 mos · New Delhi, Delhi, India

• Development of following on-chip bus VIPs for CPU sub-system and Slave-IP verification of a major mobile platform:
• 1. AMBA-AHB and AMBA-AXI VIPs
• 2. Proprietary bus
• Onsite visit for 4 months to QCOM-US to enable verification closure using multiple VIPs.

Jul 2010 – Aug 2011 · 1 yr 1 mo · New Delhi

• Worked closely on development of following VIPs:
• 1. System Verilog & OVM based proprietary VIP development
• 2. AMBA-AHB and AMBA-AXI VIP development
• All deliverables used for verification of CPU-subsystem, NoCs and slave-IP verification to lead-up of a major mobile platform development.

Sep 2008 – Jun 2010 · 1 yr 9 mos · Noida Area, India

• DDR2 Controller Verification & AMBA AXI Master Model Development:
• 1. Verification of DDR2 Controller (with AXI Slave Bridge) DUT
• 2. Development of AMBA AXI Master Model using VMM methodology
• Project Responsibility:
• Lead the verification activity in development of the verification environment.
• Lead the development of the VMM based AXI Master model.
• Integrate, simulate & debug the DUT with VMM based AXI Master model.

May 2007 – Sep 2008 · 1 yr 4 mos · Noida Area, India

• Development of multimaster multislave AMBA AHB VIP:
• 1. Developing AMBA AHB Master VIP- to be used for verification of AHB bus compliant devices
• 2. Verification of AMBA AHB Master VIP in multimaster-multislave configurations using AHB BFM VCs (AHB Slave, AHB arbiter, AHB interconnect bus, AHB protocol monitor)
• Designing AHB monitor VC
• Developing single/multi master test cases
• Functional Verification of AMBA AHB VIP (master model)
• Verification & STA for Ethernet controller IP:
• 1. Black box verification of DUT for ethernet 802.3 packets using Synopsys DW Ethernet VIP.
• 2. Static Timing Analysis of Black Box DUT & it's performance analysis.
• Project Responsibility:
• System Integration of black box DUT, PCS(Physical Coding Sublayer) core, SERDES core & Synopsys DW Ethernet VIP.
• Black box verification of DUT for ethernet 802.3 packets(corner cases) using Synopsys DW VIP.
• Development of WiMAX 2004 MAC System Model:
• 1.Study & Architecture analysis of IEEE 802.16-2004 standard.
• 2.Development of System Model for IEEE 802.16-2004 standard
• Project Responsibilty:
• Study & schedule architecture development of complete WiMAX MAC.
• Divide the MAC in module in logical sub-tops & model QoS, BW_Ranging sub-tops.