Yoav Karmon

CTO

Chicago, Illinois, United States20 yrs 9 mos experience

Key Highlights

Over 10 years of experience in FPGA-based trading systems.
Expert in low-latency networking and protocol integration.
Led multiple high-performance trading infrastructure projects.

Stackforce AI infers this person is a Fintech expert specializing in FPGA-based low-latency trading infrastructure.

Contact

Skills

Core Skills

FpgaNetworking

Other Skills

AlgorithmsAlteraAltera QuartusAssemblyCC#C++CocotbDebuggingDigital Signal ProcessorsEmbedded SoftwareEmbedded SystemsEthernetFIXField-Programmable Gate Arrays (FPGA)

About

Development low latency , FPGA based trade infrastructure: Development parsers and order sending for most US and world wide exchanges, that include text and binary based protocols. Working with research to implement trading idea into functional FPGA assisted trading platforms. Development of Free language parsing (Regx over FPGA). Development Rf support logic. Managed entire scope of projects: Board and chip selection , floor planning, development, and production management. Vast experience with timing closure issues. Edit fitting results by hand, memory and more after compilation. ML to achieve fit, full control on Vivados/Quartus settings. Creative SDC/XDC file to reach timing for designs that never met time closed before. Development of a full hardware TCP/UDP stack: UDP-TCP\IP 10G stack with inside chip latency of <50ns / TCP 32 streams. Supporting: fast re-tx, normal re-tx, dup ack, TCP KA, multicast Rx/Tx . I’ve been developing HFT Trading applications since 2010. Most systems involve FPGA and Linux server working together to bring development flexibility and high performance/low latency. 10+ years of experience at : QDR DDR SERDES 10G High speed design Multi clock design Cross clock domains Tcp IP/ UPD / MULTICAST 100% hardware 10G Ethernet TCP <-> multicast researching optic cables/copper, sfp+ modules for latency . C++ Over linux Networking Low latency design, lock less, spin locks... I've worked with almost all networking stacks for FPGA - Intilop, PLDA, LewiZ, Eynx etc...

Experience

Edgehog trading

Head of hardware engineering

Oct 2025 – Present · 5 mos · Chicago, Illinois, United States

Private trading firm

Senoir FPGA engineer

Sep 2024 – Oct 2025 · 1 yr 1 mo · Chicago, Illinois, United States

None

Non compete

Mar 2024 – Sep 2024 · 6 mos

Radix trading llc

Lead Fpga enginner

Oct 2020 – Mar 2024 · 3 yrs 5 mos

FPGA-Based Low-Latency Infrastructure Engineer | Lead Engineer
Technical Leadership: Served as lead engineer on multiple high-performance trading infrastructure projects. Provided architectural direction, mentored junior engineers, and coordinated cross-functional efforts while maintaining deep hands-on involvement in development, debugging, and optimization.
Protocol Integration & Networking: Expert in network protocols; implemented full TCP engine, MAC/IP/ARP server, and ICMP in hardware.
Built full 10G paths with GT transceivers and 322/644 MHz PCS.
Integrated TCP/UDP/MAC/PHY cores from all major FPGA vendors for ultra-low latency.
Hardware Interfaces: Worked with high-speed interfaces including QDR, DDR, PCIe, QSFP, DDQSFP, and others.
Exchange Connectivity: Interfaced with all major U.S. exchanges, parsing market data and news feeds directly on hardware.
Software Integration: Leveraged software network stacks as backends to FPGA trading engines. Enabled FPGA to inject packets into live TCP streams while software handled protocol state and non-critical processing.

Python (Programming Language)VerilogCocotbTCP/IP stackXilinxPCIe+4

Summit securities group, llc

Sr FPGA engineer

Apr 2014 – Oct 2020 · 6 yrs 6 mos · Chicago, Illinois · On-site

My main focus is FPGA based Low infrastructure.
Me experience includes:
FPGA-Based Dynamic Book: Developed a fully pipelined, dynamic limit order book on FPGA with normalized market data from multiple exchanges. Supported real-time cross-exchange aggregation, order matching insights, and flexible market views for low-latency trading strategies.
FPGA-Based Gateway: Designed and implemented a low-latency FPGA-based gateway for order entry and market data handling. Handled protocol conversion, message shaping, timestamping, and routing across multiple exchanges. Achieved deterministic latency and jitter control, with full hardware-based failover and performance monitoring.

C++FPGAGitTCP/IP stackVHDLVerilog+2

Sivron

Embedded software & FPGA team leader

Feb 2011 – Mar 2014 · 3 yrs 1 mo

My role in the company was to lead R&D of Embedded computing.
I designed multiuser FPGA-based servers.
Used FPGA to parse and re-pack data with different protocols.
interfacing with many of sivron's software services.

Iai

FPGA designer & Embedded software engineer

Apr 2005 – Dec 2010 · 5 yrs 8 mos

As an engineer, I develop CPU based systems for drones, based on NIOSII and SPOC system on FPGA platforms.
While trying to maintain low-power and high-speed design, I built fast multiplier's and dividers, stretching the FPGA to the limit and above - reaching 360MHZ divider on a startixII device! Using the SOPC builder to quickly create the system, while integrating IP cores of other vendors.
Also, I develop networking components to support several Ethernet layers.
Part of my responsibility is also writing the RT codes, HARD RT, which handles to TFTP servers, control signals, sync responsibilities of digitals&analog signals etc..., while commanding another processors or fabrics.
In addition, I develop special op-codes + HW support to improve CPU performance.
Developing HW on an FPGA (ALTERA) for drones.
Developing HW with ORCAD.
Developing RT software under UCOS (C, C++, ASM).