Abhishek Aggarwal

Software Engineer

Delhi, India9 yrs 6 mos experience

Highly Stable

Key Highlights

Expert in ASIC and SoC design methodologies.
Proficient in Verilog and low-power design techniques.
Strong experience in cross-functional team collaboration.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC architecture.

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Skills

Core Skills

System ArchitectureLow-power DesignAsic Design

Other Skills

VerilogUnified Power Format (UPF)Micro-Architecture designASICSoC FrontendMicrocontroller designFPGAsFluent in VerilogExperienced in board level designASIC Design and micro-architecture definitionSoC flowFPGA designboard designdebuggingEmbedded Systems

About

Micro-Architecture design, ASIC, SoC Frontend, Microcontroller design, FPGAs. Fluent in Verilog. Experienced in board level design. Specialties: ASIC Design and micro-architecture definition, SoC flow, FPGA design, board design, debugging.

Experience

Renesas electronics

Staff Design Engineer

Jan 2025 – Present · 1 yr 2 mos · Noida, Uttar Pradesh, India · On-site

Nxp semiconductors

2 roles

Senior Lead Design Engineer

Promoted

Apr 2023 – Jan 2025 · 1 yr 9 mos · Noida, Uttar Pradesh, India · Hybrid

Developing and maturing Design methodology as part of global methodology team to align low power flow across NXP. Defining hands-off, timelines and distribution of ownership of different deliverables to different team based on design maturity.
As Part of FE Lead responsibilities, Delivering SoC FE deliverable to all functions at different milestones with good quality assurance matrix.
Representing CRPM(Clock, Reset, Power, Mode) reviewer from SoC FE team in architectural discussions which will be used across different designs across NXP.

VerilogSystem ArchitectureUnified Power Format (UPF)Low-power Design

Lead Design Engineer

May 2021 – Apr 2023 · 1 yr 11 mos · Noida, Uttar Pradesh, India · Hybrid

This role have responsibility of designing hardware level implementation after alignment with multiple functions(Verif, Systems, BE) for any architecture requirement of SoC. Working with integration team to integrate the aligned design and work with cross functional to deliver a quality SoC.
Ownership of CRPM(Clocking, Reset, Power and mode transition) Architecture from FE team to close architecture requirement HW feasibility.
Reviewing verification plan, providing Constraints to STA team and working close with all function for full product cycle. Support EVAL team for bringing-up ASIC.

VerilogSystem Architecture

Analog devices

2 roles

Senior Digital Design Engineer

Apr 2020 – Apr 2021 · 1 yr

Verilog

Digital Design Engineer

Nov 2018 – Mar 2020 · 1 yr 4 mos

Working as Digital Design Engineer. My role in this job is to define architecture for ASIC, working for RTL development, chip-top integration, Working with Verification team for developing verification plan, Developing Firmware for chip, developing scripts, working on MATLAB for automating design and verification flow. Support EVAL team for bringing-up ASIC.

Verilog

Tejas networks

R&D Engineer

Aug 2016 – Nov 2018 · 2 yrs 3 mos · Bengaluru Area, India

Worked as R&D Engineer for Board level integration. Worked on FPGA systems, Board bring-up, scripting, assembly codes for processor and micro-controller codes. Had a full knowledge of design cycle from define architecture of product to delivering to customer.

Verilog