Ayan Roy Chowdhury

CTO

Bengaluru, Karnataka, India18 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in VLSI and ASIC design methodologies.
  • Proven leadership in engineering management roles.
  • Strong background in physical design and verification.
Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in engineering management.

Contact

LinkedIn

Skills

Core Skills

VlsiAsicStatic Timing AnalysisPhysical DesignFpgaAlgorithms

Other Skills

XilinxImage ProcessingVHDLEDACVerilogComputer ArchitectureRTL designMicroprocessorsSimulationsPerlTCLDigital Signal ProcessorsDebuggingSoC

Experience

18 yrs 10 mos
Total Experience
9 yrs 5 mos
Average Tenure
18 yrs 7 mos
Current Experience

Intel

7 roles

Principal Engineer, Director

Promoted

Mar 2024 – Present · 2 yrs 2 mos

VLSIStatic Timing AnalysisFPGAAlgorithmsXilinxImage Processing+17

Senior Engineering Manager

Jan 2020 – Feb 2024 · 4 yrs 1 mo

  • Responsible for Development & support of Sign Off Tool/Flow/Methodologies for Hard IP, SOC, Client & Server products. Expertise in RC Ext, STA, PDN signoff, EM/IR Reliability verification, ESD analysis & Physical verification runsets & flows.
RC ExtSTAPDN signoffEM/IR Reliability verificationESD analysisPhysical verification runsets+3

Engineering Manager

Promoted

Jan 2016 – Jan 2020 · 4 yrs

Sr Design Automation Engineer

May 2014 – Mar 2016 · 1 yr 10 mos

Sr Design Automation Engineer

Jul 2013 – Apr 2014 · 9 mos

Component Design Engineer

Jul 2007 – Jun 2013 · 5 yrs 11 mos

  • Worked in Design Automation and Pre Silicon validation domain in the field of Layout parasitic extraction, Electromigration and static/dynamic IRdrop analysis of P/G grids on Custom IO interfaces of multiple products in 45nm, 32nm, 22nm & 14nm processs nodes.
Layout parasitic extractionElectromigrationstatic/dynamic IRdrop analysisPhysical DesignVLSI

Intern

May 2006 – Aug 2006 · 3 mos

  • Worked on Memory Compiler development and automation of memory design methodology for different architectures.
Memory Compiler developmentautomation of memory design methodologyFPGAAlgorithms

Education

Indian Statistical Institute, Kolkata

M.Tech — Computer Science

Jan 2005 – Jan 2007

Jadavpur University

BE — Electrical Engineering

Jan 2001 – Jan 2005

St. Xavier's College (Autonomous), Kolkata

Jan 1999 – Jan 2001

Baranagar R.K.M High School

Jan 1999 – Present

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