Pankaj Sharma — Director of Engineering

Pankaj Sharma- Sr. R&D Manager Engineer with 13+ years of Exp. in VIP Development Project Details : * Working on Display Port VIP(DP 1.4/2.0, Test suiites ) and USB4 DP Tunneling VIPs (System Verilog - UVM) (Dec'19 - Present) * Worked on GDDR6 VIP (Mar'18 - Dec'19) (System Verilog - UVM)(1 Year and 9 Months) * Worked on LPDDR5/LPDDR4 VIP (System Verilog - UVM) (Mar'17 - Mar'18) (1 Year) * Worked on Hyperflash Transactor (Verilog RTL Coding) (Aug'16 - Mar'17) (7 Months) * Worked on EMMC/SD/SDIO/UHS2 VIPs & Testsuites (System Verilog - UVM) (Aug'14 - Jul'16) (2 Years) * Worked on LPDDR2/3/4 & GDDR Memory VIPs (System Verilog - UVM/OVM) (Aug'13 - Jul'14) (1 Year) * Worked on SD/SDIO VIP (Verilog BFM & System Verilog Wrapper) (Apr'11 - July'13) (2 years and 2 Months) SKILL SET: - Language: C, C++, VHDL, Verilog, SystemVerilog - Verification Methodologies: OVM, UVM - Simulation Tools Used: Model Sim, VCS, NC Verilog - Debugging Tools Used: Verdi, DVE, Simvision Role/Responsibilities :- * R&D owner for GDDR6 VIP Product * Managing Verification Team * Key BFM’s features implementation in System Verilog and Verilog. * Involved in test suite environment * BFM’s Architecture design and FSM implementations. * Worked on Checkers, Scoreboarding, Testbenches/Environments creation, Callback support, Exception mechanism etc. * Code maintenance, Bug fixing and Simprofiling for controlling memory leakage and better time performance. * Worked on Functional Coverage and constraints based System Randomization for configuration, transaction and other data classes. * Worked on Error Exception mechanisms. * Worked on Sequences/Test Cases in UVM/OVM. * Worked on Compliance Test Cases in Verilog. * Worked on Test Suite RAL model. * Integration of VIPs with IIPs. * Prepared Test Plans, Coverage Plans, Checker Plans & Design Documents. * Customer interaction for the Product’s Evaluations, Integration and Support Cases.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in developing verification IP.

Experience: 17 yrs 6 mos