Ravi Teja Lolla

DevOps Engineer

Bengaluru, Karnataka, India9 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Functional Verification and ASIC Design.
Proven track record in high-speed memory PHY IP verification.
Strong background in mixed-signal and RTL verification.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and mixed-signal design.

Contact

ravitejalolla.rtl@gmail.com LinkedIn

Skills

Core Skills

Functional VerificationAsic Design

Other Skills

RTLGLSNLPMixed-signalSVUVMMetric Driven Verificatione/SPECMANCSystem VerilogLinuxUniversal Verification Methodology (UVM)Very-Large-Scale Integration (VLSI)SimulationsMixed Signal

About

Areas of interest broadly include IP Verification, Computer Architecture and ASIC/SoC Design. Skill Set: Programming Languages – C HDLs - Verilog, System Verilog Methodology – UVM Simulation Tools – Verdi, NCSim, Modelsim Protocols – I2C, SPI, UART, APB, Ethernet PHY layer, PCIe PHY layer Scripting - Perl, Shell

Experience

Amd

3 roles

Member of Technical Staff

Jul 2024 – Present · 1 yr 8 mos

Sr. Silicon Design Engineer

Jul 2019 – Jun 2024 · 4 yrs 11 mos

DV for next-gen Graphics high speed memory PHY IPs
DV cuts across RTL, GLS, NLP and Mixed-signal co-simulations

Design Engineer 2

Apr 2018 – Jun 2019 · 1 yr 2 mos

DV for next-gen Graphics high speed memory PHY IPs
DV across RTL, GLS, NLP, Mixed-signal cosims and Coverage closure

Texas instruments

4 roles

Digital Design Engineer

Jan 2018 – Mar 2018 · 2 mos · Bengaluru Area, India

Project - PCIe Retimer PHY
Developed sequences/testcases for design features - loopback, compliance testing etc.
Drove metric driven verification(MDV) approach for the project while setting up verif environment for code and functional coverage analysis(using Cadence's Integrated Metric Center).
Environment – SV/UVM

Digital Design Engineer

Oct 2017 – Dec 2017 · 2 mos · Bengaluru Area, India

Project - Ethernet PHY
Owned verification of features like
Auto-negotiation(back-to-back PHYs) in different modes of operation
Corner/edge case scenarios like Interrupts generation and testing
Register accesses in all possible modes of operation for the EPHY.
Environment – e/SPECMAN

Digital Design Engineer

Apr 2017 – Sep 2017 · 5 mos · Bengaluru Area, India

Project - PCIe Retimer PHY
Developed the subsystem level verification environment for the PCIe Retimer (PHY layer)
Verification of Physical Coding Sub-layer(PCS) block for the PCIe PHY
Sequences/testcases development to address data-path functionality through different design features like lane reversal, polarity inversion etc.
Regression automation, debug and convergence
Environment – SV/UVM

Digital Design Engineer

Jul 2016 – Mar 2017 · 8 mos · Bengaluru Area, India

Project - Ethernet Switch
Verification of legacy switch features like Power on Reset, basic register accesses for multiple IPs(GPIO, UART, SPI, I2C) in the switch top and other subsystems which constituted the SoC.
Regression tracking/debug/closure.
Development/debug for BOOT ROM tests in different modes of operation.
Generated patterns for reset and clock debug(DFT specific) for different modules for post Silicon validation of the switch during bring-up.
Environment – All are C based test cases since it involved a processor also

Nvidia

Hardware Verification Intern

Jan 2016 – Jun 2016 · 5 mos · Bengaluru Area, India

Functional verification of Direct Memory Access (DMA) for 'Xavier' PCIe architecture.
Experimented and Configured DMA to undertake different types of data transfers.
Several configurations like single/multi-channel accesses, Linked lists (normal/circular), initialization by local/remote CPU and a few advanced cases like error handling and interrupt generation have been thoroughly coded and functionally verified.
Environment - C/System Verilog