Yashdeep Godhal

DevOps Engineer

Bengaluru, Karnataka, India18 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

13 years of experience in ASIC Design and Verification.
Led a team of 10+ engineers in functional verification.
Hands-on experience with multiple verification methodologies.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with extensive ASIC design and verification experience.

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Skills

Other Skills

SpecmanDDR2AMBA AHBLogic SynthesisASICUVMI2CVeraAXITiming ClosureSoCVLSIRTL CodingRTL Design

About

Design and Verification Engineer with 13 years of experience in ASIC Design, Verification and Synthesis. Responsibilities have included all aspects of Front End Design flow i.e.Architecture, RTL Coding, Integration, Functional Verification as well as Formal Verification, and Synthesis. Also worked on IP development, integration, synthesis and verification. Specialties: -Experience in Functional Verification of ASICs/FPGAs -Experience in leading team of 10+ engineers. -Hands on experience in languages like Verilog, SystemVerilog and C++ and methodologies like OVM, VMM, UVM -Hands on experience on verification of LPDDR2/3, Ethernet, Bus protocols, Serial Interface Protocols, Memory Management Unit, Processors -Execution experience in both Offshore/Onsite engagement model Languages: Verilog, System Verilog, e Verification Language, Vera, Perl, Synthesis Scripts, C/C++ Methodology: eRM, OVM, VMM, UVM Protocols - Serial and Parallel Interfaces, Ethernet, LPDDR2, Bus protocols (AHB, APB, AXI)

Experience

18 yrs 10 mos

Total Experience

2 yrs 8 mos

Average Tenure

6 yrs 9 mos

Current Experience

Edgeq inc.

DV Engineer

Jul 2019 – Present · 6 yrs 9 mos

Intel corporation

Validation Lead

Apr 2018 – Jun 2019 · 1 yr 2 mos · Bengaluru Area, India

Validation lead for Modem Sub-system

Qualcomm

2 roles

Senior Staff Engineer

Nov 2017 – Apr 2018 · 5 mos

Memory Management Unit IP DV

Staff Engineer

Mar 2015 – Nov 2017 · 2 yrs 8 mos

Verification of Memory Management Unit Sub System across Multiple Projects

Bangalore

ASIC Design & Verification Consultant

Jan 2013 – Mar 2015 · 2 yrs 2 mos · Bengaluru Area, India

Worked on functional verification of multiple blocks for high speed networking ASIC.
Worked on verification at top/gate/package level for multiple generations of above ASIC.
Verification for blocks/top level for Image processing chip

Qualcomm

2 roles

Senior Lead Engineer

Apr 2012 – Jan 2013 · 9 mos

Worked on functional verification of next generation bus integrated memory controllers for LPDDR2/3.

Senior Engineer

Nov 2010 – Mar 2012 · 1 yr 4 mos

Worked on functional verification of different blocks in advanced multimode 4G modem as a part of modem DV team.
Worked on functional and formal verification of multiple components in bus reusable components, bus-bridges and profiling monitors for various chips.

Chip design (pvt) ltd

Senior Engineer

Jan 2010 – Oct 2010 · 9 mos · Gurgaon, India

Worked on mainly MAC layer of 4G-chip for an industry leader. I worked on design and verification of Boot-loader, GPIO. I also worked on integration and functional verification of I2C and Ethernet MAC IPs.
Worked with another industry leader for designing modules specific to emulation tool development.

Ist austria

Visiting Researcher

Oct 2009 – Dec 2009 · 2 mos · Austria

Worked on high level synthesis from formal specifications.

Chip design (pvt) ltd

Design Engineer

Nov 2006 – Jun 2009 · 2 yrs 7 mos · Gurgaon, India

Design, Verification, Synthesis and Timing closure for AHB master/slave and serial interfaces SPI, I2C and TS-IF.
Functional Verification of Time Domain Processor and blocks in Channel Estimator.
Development of in-house Signal Processing IPs for latest standard in communication. It consisted of full front-end design cycle i.e. starting from architecture to netlist.

Tata motors

Assistant Manager

Jul 2006 – Oct 2006 · 3 mos

Assisted launch of LPK 407 Tipper while working as an assistant manager in New Product Introduction Department.

University of calabria

Summer Internship

May 2005 – Jul 2005 · 2 mos

In the project named “Constrained Monitoring and Supervision for Networked Power Systems”, I developed and simulated new strategies for constrained supervision of networked power systems. With application of these strategies, the deviations in tie line power and frequency due to load-disturbances were minimized.