Upendra Sachan

Software Engineer

Bengaluru, Karnataka, India14 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC and SOC verification methodologies.
  • Proficient in multiple hardware description languages.
  • Strong background in developing verification environments.
Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC and SOC design.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationAsic Verification

Other Skills

AMBA AHBClearCaseEMMCI2CPCIPerlRTL designSDSDIOSPISpecmanSystem on a Chip (SoC)SystemVerilogTJETUSB 3.0

Experience

Marvell technology

Principal Engineer

Jun 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India · Hybrid

Qualcomm

2 roles

Staff Engineer

Dec 2020 – Jun 2024 · 3 yrs 6 mos

Sr lead engineer

May 2018 – Nov 2020 · 2 yrs 6 mos

Intel corporation

Verification Engineer

Jul 2016 – May 2018 · 1 yr 10 mos · bangalore

Synopsys

R & D Engineer

Jul 2014 – May 2016 · 1 yr 10 mos · Banglore

Wipro technologies

ASIC verification engineer

May 2011 – Jul 2014 · 3 yrs 2 mos · Pune Area, India

  • Development of Verification components for verification of SOC/ASIC Blocks
  • Devlopment of Verification enviroment In system verilog and specman.
  • Tools-Cadence's Specman and Rational Clearcase for Version System on Unix Platform ,VCS, DVE
  • Good knowledge in EMMC,SD,SDIO card.
  • Understanding of SOC project with i2c,spi,ocp,pci,emmc,usb3.0,msi generator,interrupt module and protocal.
  • Understanding of asic power chip .
SystemVerilogSpecmanUnixVLSIEMMCSD+7

Education

cdac

PG DIPLOMA IN VLSI

Jan 2010 – Jan 2011

Dr. A.P.J. Abdul Kalam Technical University

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2006 – Jan 2010

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